From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=36805 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PqCbc-0006Pl-WD for qemu-devel@nongnu.org; Thu, 17 Feb 2011 17:45:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PqCbZ-0000WO-Ie for qemu-devel@nongnu.org; Thu, 17 Feb 2011 17:45:48 -0500 Received: from mail.serverraum.org ([78.47.150.89]:48592) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PqCbZ-0000Vk-7u for qemu-devel@nongnu.org; Thu, 17 Feb 2011 17:45:45 -0500 From: Michael Walle Date: Thu, 17 Feb 2011 23:45:06 +0100 Message-Id: <1297982718-21865-6-git-send-email-michael@walle.cc> In-Reply-To: <1297982718-21865-1-git-send-email-michael@walle.cc> References: <1297982718-21865-1-git-send-email-michael@walle.cc> Subject: [Qemu-devel] [PATCH 05/17] lm32: gdbstub support List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , "Edgar E. Iglesias" , Michael Walle , Alexander Graf , Richard Henderson This patch adds lm32 support to the gdbstub. Signed-off-by: Michael Walle --- gdbstub.c | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 76 insertions(+), 0 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index ed51a8a..1e9f931 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1462,6 +1462,80 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) return r; } +#elif defined (TARGET_LM32) + +#include "hw/lm32_pic.h" +#define NUM_CORE_REGS (32 + 7) + +static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + GET_REG32(env->regs[n]); + } else { + switch (n) { + case 32: + GET_REG32(env->pc); + break; + /* FIXME: put in right exception ID */ + case 33: + GET_REG32(0); + break; + case 34: + GET_REG32(env->eba); + break; + case 35: + GET_REG32(env->deba); + break; + case 36: + GET_REG32(env->ie); + break; + case 37: + GET_REG32(lm32_pic_get_im(env->pic_state)); + break; + case 38: + GET_REG32(lm32_pic_get_ip(env->pic_state)); + break; + } + } + return 0; +} + +static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) +{ + uint32_t tmp; + + if (n > NUM_CORE_REGS) { + return 0; + } + + tmp = ldl_p(mem_buf); + + if (n < 32) { + env->regs[n] = tmp; + } else { + switch (n) { + case 32: + env->pc = tmp; + break; + case 34: + env->eba = tmp; + break; + case 35: + env->deba = tmp; + break; + case 36: + env->ie = tmp; + break; + case 37: + lm32_pic_set_im(env->pic_state, tmp); + break; + case 38: + lm32_pic_set_ip(env->pic_state, tmp); + break; + } + } + return 4; +} #else #define NUM_CORE_REGS 0 @@ -1737,6 +1811,8 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc) #elif defined (TARGET_S390X) cpu_synchronize_state(s->c_cpu); s->c_cpu->psw.addr = pc; +#elif defined (TARGET_LM32) + s->c_cpu->pc = pc; #endif } -- 1.7.2.3