From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=45173 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PrTBu-0000O3-SC for qemu-devel@nongnu.org; Mon, 21 Feb 2011 05:40:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PrTBr-0000H0-Sz for qemu-devel@nongnu.org; Mon, 21 Feb 2011 05:40:30 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:43715) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PrTBr-0000Ee-KJ for qemu-devel@nongnu.org; Mon, 21 Feb 2011 05:40:27 -0500 From: Peter Maydell Date: Mon, 21 Feb 2011 10:40:17 +0000 Message-Id: <1298284818-16504-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1298284818-16504-1-git-send-email-peter.maydell@linaro.org> References: <1298284818-16504-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 1/2] target-arm: Refactor to pull narrowing decode into separate function List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org Pull the code which decodes narrowing operations as being either signed/unsigned saturate or plain out into its own function. Signed-off-by: Peter Maydell --- target-arm/translate.c | 45 +++++++++++++++++++-------------------------- 1 files changed, 19 insertions(+), 26 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 5f377a4..fa20e84 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4164,6 +4164,23 @@ static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u) } } +static void gen_neon_narrow_op(int op, int u, int size, TCGv dest, TCGv_i64 src) +{ + if (op) { + if (u) { + gen_neon_unarrow_sats(size, dest, src); + } else { + gen_neon_narrow(size, dest, src); + } + } else { + if (u) { + gen_neon_narrow_satu(size, dest, src); + } else { + gen_neon_narrow_sats(size, dest, src); + } + } +} + /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. We process data in a mixture of 32-bit and 64-bit chunks. @@ -4839,19 +4856,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) dead_tmp(tmp3); } tmp = new_tmp(); - if (op == 8) { - if (u) { /* VQSHRUN / VQRSHRUN */ - gen_neon_unarrow_sats(size - 1, tmp, cpu_V0); - } else { /* VSHRN / VRSHRN */ - gen_neon_narrow(size - 1, tmp, cpu_V0); - } - } else { - if (u) { /* VQSHRN / VQRSHRN */ - gen_neon_narrow_satu(size - 1, tmp, cpu_V0); - } else { /* VQSHRN / VQRSHRN */ - gen_neon_narrow_sats(size - 1, tmp, cpu_V0); - } - } + gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0); neon_store_reg(rd, pass, tmp); } /* for pass */ if (size == 3) { @@ -5439,19 +5444,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) for (pass = 0; pass < 2; pass++) { neon_load_reg64(cpu_V0, rm + pass); tmp = new_tmp(); - if (op == 36) { - if (q) { /* VQMOVUN */ - gen_neon_unarrow_sats(size, tmp, cpu_V0); - } else { /* VMOVN */ - gen_neon_narrow(size, tmp, cpu_V0); - } - } else { /* VQMOVN */ - if (q) { - gen_neon_narrow_satu(size, tmp, cpu_V0); - } else { - gen_neon_narrow_sats(size, tmp, cpu_V0); - } - } + gen_neon_narrow_op(op == 36, q, size, tmp, cpu_V0); if (pass == 0) { tmp2 = tmp; } else { -- 1.7.1