Re: [PATCH 01/10] target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows

[Richard Henderson <richard.henderson@linaro.org>]

On 8/11/22 10:16, Peter Maydell wrote:
> When the cycle counter overflows, we are intended to set bit 31 in PMOVSR
> to indicate this. However a missing ULL suffix means that we end up
> setting all of bits 63-31. Fix the bug.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/arm/helper.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index d7bc467a2a5..87c89748954 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1186,7 +1186,7 @@ static void pmccntr_op_start(CPUARMState *env)
>           uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
>                                    1ull << 63 : 1ull << 31;
>           if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) {
> -            env->cp15.c9_pmovsr |= (1 << 31);
> +            env->cp15.c9_pmovsr |= (1ULL << 31);
>               pmu_update_irq(env);
>           }
>   
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~