* [Qemu-devel] [PATCH] target-arm: Handle VMOV between two core and VFP single regs
@ 2011-03-01 17:35 Peter Maydell
2011-03-06 19:29 ` Aurelien Jarno
0 siblings, 1 reply; 2+ messages in thread
From: Peter Maydell @ 2011-03-01 17:35 UTC (permalink / raw)
To: qemu-devel; +Cc: patches
Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and
VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a
pair of VFP single precision registers):
* An incorrect condition meant these instruction patterns were being
treated as load/store multiple, which resulted in the generation
of bad code and a runtime segfault
* The order of the core register pair was reversed so the values would
go to the wrong registers
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index dbd958b..0111a61 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -3232,7 +3232,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
break;
case 0xc:
case 0xd:
- if (dp && (insn & 0x03e00000) == 0x00400000) {
+ if ((insn & 0x03e00000) == 0x00400000) {
/* two-register transfer */
rn = (insn >> 16) & 0xf;
rd = (insn >> 12) & 0xf;
@@ -3254,10 +3254,10 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
} else {
gen_mov_F0_vreg(0, rm);
tmp = gen_vfp_mrs();
- store_reg(s, rn, tmp);
+ store_reg(s, rd, tmp);
gen_mov_F0_vreg(0, rm + 1);
tmp = gen_vfp_mrs();
- store_reg(s, rd, tmp);
+ store_reg(s, rn, tmp);
}
} else {
/* arm->vfp */
@@ -3269,10 +3269,10 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
gen_vfp_msr(tmp);
gen_mov_vreg_F0(0, rm * 2 + 1);
} else {
- tmp = load_reg(s, rn);
+ tmp = load_reg(s, rd);
gen_vfp_msr(tmp);
gen_mov_vreg_F0(0, rm);
- tmp = load_reg(s, rd);
+ tmp = load_reg(s, rn);
gen_vfp_msr(tmp);
gen_mov_vreg_F0(0, rm + 1);
}
--
1.7.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH] target-arm: Handle VMOV between two core and VFP single regs
2011-03-01 17:35 [Qemu-devel] [PATCH] target-arm: Handle VMOV between two core and VFP single regs Peter Maydell
@ 2011-03-06 19:29 ` Aurelien Jarno
0 siblings, 0 replies; 2+ messages in thread
From: Aurelien Jarno @ 2011-03-06 19:29 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, patches
On Tue, Mar 01, 2011 at 05:35:19PM +0000, Peter Maydell wrote:
> Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and
> VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a
> pair of VFP single precision registers):
>
> * An incorrect condition meant these instruction patterns were being
> treated as load/store multiple, which resulted in the generation
> of bad code and a runtime segfault
> * The order of the core register pair was reversed so the values would
> go to the wrong registers
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/translate.c | 10 +++++-----
> 1 files changed, 5 insertions(+), 5 deletions(-)
Thanks, applied.
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index dbd958b..0111a61 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -3232,7 +3232,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
> break;
> case 0xc:
> case 0xd:
> - if (dp && (insn & 0x03e00000) == 0x00400000) {
> + if ((insn & 0x03e00000) == 0x00400000) {
> /* two-register transfer */
> rn = (insn >> 16) & 0xf;
> rd = (insn >> 12) & 0xf;
> @@ -3254,10 +3254,10 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
> } else {
> gen_mov_F0_vreg(0, rm);
> tmp = gen_vfp_mrs();
> - store_reg(s, rn, tmp);
> + store_reg(s, rd, tmp);
> gen_mov_F0_vreg(0, rm + 1);
> tmp = gen_vfp_mrs();
> - store_reg(s, rd, tmp);
> + store_reg(s, rn, tmp);
> }
> } else {
> /* arm->vfp */
> @@ -3269,10 +3269,10 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
> gen_vfp_msr(tmp);
> gen_mov_vreg_F0(0, rm * 2 + 1);
> } else {
> - tmp = load_reg(s, rn);
> + tmp = load_reg(s, rd);
> gen_vfp_msr(tmp);
> gen_mov_vreg_F0(0, rm);
> - tmp = load_reg(s, rd);
> + tmp = load_reg(s, rn);
> gen_vfp_msr(tmp);
> gen_mov_vreg_F0(0, rm + 1);
> }
> --
> 1.7.1
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
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