From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=33726 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PvJIS-0004Hz-35 for qemu-devel@nongnu.org; Thu, 03 Mar 2011 19:55:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PvJIQ-0002vC-Pr for qemu-devel@nongnu.org; Thu, 03 Mar 2011 19:55:07 -0500 Received: from mail-fx0-f45.google.com ([209.85.161.45]:38187) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PvJIQ-0002uu-LR for qemu-devel@nongnu.org; Thu, 03 Mar 2011 19:55:06 -0500 Received: by mail-fx0-f45.google.com with SMTP id 11so1838038fxm.4 for ; Thu, 03 Mar 2011 16:55:06 -0800 (PST) From: Dmitry Eremin-Solenikov Date: Fri, 4 Mar 2011 03:54:59 +0300 Message-Id: <1299200099-22482-2-git-send-email-dbaryshkov@gmail.com> In-Reply-To: <1299200099-22482-1-git-send-email-dbaryshkov@gmail.com> References: <1299200099-22482-1-git-send-email-dbaryshkov@gmail.com> Subject: [Qemu-devel] [PATCH 2/2] mainstone: PCMCIA support List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Extend mst_fpga and mainstone with logic to support PCMCIA attachment (IRQs, status regs). Signed-off-by: Dmitry Eremin-Solenikov --- hw/mainstone.c | 7 +++++++ hw/mst_fpga.c | 29 +++++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/hw/mainstone.c b/hw/mainstone.c index 8970dd8..50691ca 100644 --- a/hw/mainstone.c +++ b/hw/mainstone.c @@ -149,6 +149,13 @@ static void mainstone_common_init(ram_addr_t ram_size, /* MMC/SD host */ pxa2xx_mmci_handlers(cpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ)); + pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0], + qdev_get_gpio_in(mst_irq, S0_IRQ), + qdev_get_gpio_in(mst_irq, S0_CD_IRQ)); + pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1], + qdev_get_gpio_in(mst_irq, S1_IRQ), + qdev_get_gpio_in(mst_irq, S1_CD_IRQ)); + smc91c111_init(&nd_table[0], MST_ETH_PHYS, qdev_get_gpio_in(mst_irq, ETHERNET_IRQ)); diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c index 407bac9..9ee415e 100644 --- a/hw/mst_fpga.c +++ b/hw/mst_fpga.c @@ -26,6 +26,12 @@ #define MST_PCMCIA0 0xe0 #define MST_PCMCIA1 0xe4 +#define MST_PCMCIAx_READY (1 << 10) +#define MST_PCMCIAx_nCD (1 << 5) + +#define MST_PCMCIA_CD0_IRQ 9 +#define MST_PCMCIA_CD1_IRQ 13 + typedef struct mst_irq_state{ SysBusDevice busdev; @@ -57,6 +63,21 @@ mst_fpga_set_irq(void *opaque, int irq, int level) else s->prev_level &= ~(1u << irq); + switch(irq) { + case MST_PCMCIA_CD0_IRQ: + if (level) + s->pcmcia0 &= ~MST_PCMCIAx_nCD; + else + s->pcmcia0 |= MST_PCMCIAx_nCD; + break; + case MST_PCMCIA_CD1_IRQ: + if (level) + s->pcmcia1 &= ~MST_PCMCIAx_nCD; + else + s->pcmcia1 |= MST_PCMCIAx_nCD; + break; + } + if ((s->intmskena & (1u << irq)) && level) s->intsetclr |= 1u << irq; @@ -141,11 +162,12 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) s->intsetclr = (value & 0xFEEFF); qemu_set_irq(s->parent, s->intsetclr & s->intmskena); break; + /* For PCMCIAx allow the to change only power and reset */ case MST_PCMCIA0: - s->pcmcia0 = value; + s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f); break; case MST_PCMCIA1: - s->pcmcia1 = value; + s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f); break; default: printf("Mainstone - mst_fpga_writeb: Bad register offset " @@ -180,6 +202,9 @@ static int mst_fpga_init(SysBusDevice *dev) s = FROM_SYSBUS(mst_irq_state, dev); + s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD; + s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD; + sysbus_init_irq(dev, &s->parent); /* alloc the external 16 irqs */ -- 1.7.2.3