[Qemu-devel] [PATCH v3 0/2] ARM: Add Versatile Express board model

[Qemu-devel] [PATCH v3 0/2] ARM: Add Versatile Express board model

[Peter Maydell]

This patchset adds support for the ARM Versatile Express board
with Cortex-A9 daughterboard. It's based on some vexpress modelling
work done by Bahadir Balban and Amit Mahajan at B Labs, overhauled
and cleaned up by me (thanks to them for making that work available).

(The MMC changes this patch depends on are now in qemu git master,
so this v3 is a standalone patchset.)

Changes v1->v2:
 * bump the vmstate version on arm_sysctl, as suggested by Juan Quintela
Changes v2->v3:
 * allow arm_sysctl vmstate loads from v1, as suggested by Paolo Bonzini
 * add sys_mci to the vmstate while we are bumping the version number
 * handling of secondary CPU reset has moved into hw/arm_boot.c 

Peter Maydell (2):
  hw/arm_sysctl.c: Add the Versatile Express system registers
  hw/vexpress.c: Add model of ARM Versatile Express board

 Makefile.target |    1 +
 hw/arm_sysctl.c |   64 ++++++++++++++++-
 hw/vexpress.c   |  224 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 288 insertions(+), 1 deletions(-)
 create mode 100644 hw/vexpress.c

[Qemu-devel] [PATCH v3 1/2] hw/arm_sysctl.c: Add the Versatile Express system registers

[Peter Maydell]

Add support for the Versatile Express SYS_CFG registers, which provide
a generic means of reading or writing configuration information from
various parts of the board. We only implement shutdown and reset.

Also make the RESETCTL register RAZ/WI on Versatile Express rather
than reset the board. Other system registers are generally the same
as Versatile and Realview.

This includes a VMState version number bump for arm_sysctl,
since we have new register state to preserve. It also adds
sys_mci to the VMState while we're bumping the version number
(an accidental omission from commit b50ff6f5).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm_sysctl.c |   64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 63 insertions(+), 1 deletions(-)

diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index 799b007..b1110b4 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -27,11 +27,14 @@ typedef struct {
     uint32_t resetlevel;
     uint32_t proc_id;
     uint32_t sys_mci;
+    uint32_t sys_cfgdata;
+    uint32_t sys_cfgctrl;
+    uint32_t sys_cfgstat;
 } arm_sysctl_state;
 
 static const VMStateDescription vmstate_arm_sysctl = {
     .name = "realview_sysctl",
-    .version_id = 1,
+    .version_id = 2,
     .minimum_version_id = 1,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(leds, arm_sysctl_state),
@@ -41,6 +44,10 @@ static const VMStateDescription vmstate_arm_sysctl = {
         VMSTATE_UINT32(flags, arm_sysctl_state),
         VMSTATE_UINT32(nvflags, arm_sysctl_state),
         VMSTATE_UINT32(resetlevel, arm_sysctl_state),
+        VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
+        VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
+        VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
+        VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -53,6 +60,7 @@ static const VMStateDescription vmstate_arm_sysctl = {
 #define BOARD_ID_EB 0x140
 #define BOARD_ID_PBA8 0x178
 #define BOARD_ID_PBX 0x182
+#define BOARD_ID_VEXPRESS 0x190
 
 static int board_id(arm_sysctl_state *s)
 {
@@ -104,6 +112,10 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
     case 0x38: /* NVFLAGS */
         return s->nvflags;
     case 0x40: /* RESETCTL */
+        if (board_id(s) == BOARD_ID_VEXPRESS) {
+            /* reserved: RAZ/WI */
+            return 0;
+        }
         return s->resetlevel;
     case 0x44: /* PCICTL */
         return 1;
@@ -142,7 +154,23 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
     case 0xcc: /* SYS_TEST_OSC3 */
     case 0xd0: /* SYS_TEST_OSC4 */
         return 0;
+    case 0xa0: /* SYS_CFGDATA */
+        if (board_id(s) != BOARD_ID_VEXPRESS) {
+            goto bad_reg;
+        }
+        return s->sys_cfgdata;
+    case 0xa4: /* SYS_CFGCTRL */
+        if (board_id(s) != BOARD_ID_VEXPRESS) {
+            goto bad_reg;
+        }
+        return s->sys_cfgctrl;
+    case 0xa8: /* SYS_CFGSTAT */
+        if (board_id(s) != BOARD_ID_VEXPRESS) {
+            goto bad_reg;
+        }
+        return s->sys_cfgstat;
     default:
+    bad_reg:
         printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
         return 0;
     }
@@ -190,6 +218,10 @@ static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
         s->nvflags &= ~val;
         break;
     case 0x40: /* RESETCTL */
+        if (board_id(s) == BOARD_ID_VEXPRESS) {
+            /* reserved: RAZ/WI */
+            break;
+        }
         if (s->lockval == LOCK_VALUE) {
             s->resetlevel = val;
             if (val & 0x100)
@@ -216,7 +248,37 @@ static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
     case 0x98: /* OSCRESET3 */
     case 0x9c: /* OSCRESET4 */
         break;
+    case 0xa0: /* SYS_CFGDATA */
+        if (board_id(s) != BOARD_ID_VEXPRESS) {
+            goto bad_reg;
+        }
+        s->sys_cfgdata = val;
+        return;
+    case 0xa4: /* SYS_CFGCTRL */
+        if (board_id(s) != BOARD_ID_VEXPRESS) {
+            goto bad_reg;
+        }
+        s->sys_cfgctrl = val & ~(3 << 18);
+        s->sys_cfgstat = 1;            /* complete */
+        switch (s->sys_cfgctrl) {
+        case 0xc0800000:            /* SYS_CFG_SHUTDOWN to motherboard */
+            qemu_system_shutdown_request();
+            break;
+        case 0xc0900000:            /* SYS_CFG_REBOOT to motherboard */
+            qemu_system_reset_request();
+            break;
+        default:
+            s->sys_cfgstat |= 2;        /* error */
+        }
+        return;
+    case 0xa8: /* SYS_CFGSTAT */
+        if (board_id(s) != BOARD_ID_VEXPRESS) {
+            goto bad_reg;
+        }
+        s->sys_cfgstat = val & 3;
+        return;
     default:
+    bad_reg:
         printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
         return;
     }
-- 
1.7.1

[Qemu-devel] [PATCH v3 2/2] hw/vexpress.c: Add model of ARM Versatile Express board

[Peter Maydell]

Add a model of the ARM Versatile Express board (with A9MPx4
daughterboard).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 Makefile.target |    1 +
 hw/vexpress.c   |  224 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 225 insertions(+), 0 deletions(-)
 create mode 100644 hw/vexpress.c

diff --git a/Makefile.target b/Makefile.target
index 220589e..949bd4e 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -315,6 +315,7 @@ obj-arm-y += framebuffer.o
 obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
 obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
 obj-arm-y += syborg_virtio.o
+obj-arm-y += vexpress.o
 
 obj-sh4-y = shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
 obj-sh4-y += sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o
diff --git a/hw/vexpress.c b/hw/vexpress.c
new file mode 100644
index 0000000..9ffd332
--- /dev/null
+++ b/hw/vexpress.c
@@ -0,0 +1,224 @@
+/*
+ * ARM Versatile Express emulation.
+ *
+ * Copyright (c) 2010 - 2011 B Labs Ltd.
+ * Copyright (c) 2011 Linaro Limited
+ * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sysbus.h"
+#include "arm-misc.h"
+#include "primecell.h"
+#include "devices.h"
+#include "net.h"
+#include "sysemu.h"
+#include "boards.h"
+
+#define SMP_BOOT_ADDR 0xe0000000
+
+#define VEXPRESS_BOARD_ID 0x8e0
+
+static struct arm_boot_info vexpress_binfo = {
+    .smp_loader_start = SMP_BOOT_ADDR,
+};
+
+static void vexpress_a9_init(ram_addr_t ram_size,
+                     const char *boot_device,
+                     const char *kernel_filename, const char *kernel_cmdline,
+                     const char *initrd_filename, const char *cpu_model)
+{
+    CPUState *env = NULL;
+    ram_addr_t ram_offset, vram_offset, sram_offset;
+    DeviceState *dev, *sysctl;
+    SysBusDevice *busdev;
+    qemu_irq *irqp;
+    qemu_irq pic[64];
+    int n;
+    qemu_irq cpu_irq[4];
+    uint32_t proc_id;
+    uint32_t sys_id;
+    ram_addr_t low_ram_size, vram_size, sram_size;
+
+    if (!cpu_model) {
+        cpu_model = "cortex-a9";
+    }
+
+    for (n = 0; n < smp_cpus; n++) {
+        env = cpu_init(cpu_model);
+        if (!env) {
+            fprintf(stderr, "Unable to find CPU definition\n");
+            exit(1);
+        }
+        irqp = arm_pic_init_cpu(env);
+        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
+    }
+
+    if (ram_size > 0x40000000) {
+        /* 1GB is the maximum the address space permits */
+        fprintf(stderr, "vexpress: cannot model more than 1GB RAM\n");
+        exit(1);
+    }
+
+    ram_offset = qemu_ram_alloc(NULL, "vexpress.highmem", ram_size);
+    low_ram_size = ram_size;
+    if (low_ram_size > 0x4000000) {
+        low_ram_size = 0x4000000;
+    }
+    /* RAM is from 0x60000000 upwards. The bottom 64MB of the
+     * address space should in theory be remappable to various
+     * things including ROM or RAM; we always map the RAM there.
+     */
+    cpu_register_physical_memory(0x0, low_ram_size, ram_offset | IO_MEM_RAM);
+    cpu_register_physical_memory(0x60000000, ram_size,
+                                 ram_offset | IO_MEM_RAM);
+
+    /* 0x1e000000 A9MPCore (SCU) private memory region */
+    dev = qdev_create(NULL, "a9mpcore_priv");
+    qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
+    qdev_init_nofail(dev);
+    busdev = sysbus_from_qdev(dev);
+    vexpress_binfo.smp_priv_base = 0x1e000000;
+    sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base);
+    for (n = 0; n < smp_cpus; n++) {
+        sysbus_connect_irq(busdev, n, cpu_irq[n]);
+    }
+    /* Interrupts [42:0] are from the motherboard;
+     * [47:43] are reserved; [63:48] are daughterboard
+     * peripherals. Note that some documentation numbers
+     * external interrupts starting from 32 (because the
+     * A9MP has internal interrupts 0..31).
+     */
+    for (n = 0; n < 64; n++) {
+        pic[n] = qdev_get_gpio_in(dev, n);
+    }
+
+    /* Motherboard peripherals CS7 : 0x10000000 .. 0x10020000 */
+    sys_id = 0x1190f500;
+    proc_id = 0x0c000191;
+
+    /* 0x10000000 System registers */
+    sysctl = qdev_create(NULL, "realview_sysctl");
+    qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
+    qdev_init_nofail(sysctl);
+    qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
+    sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
+
+    /* 0x10001000 SP810 system control */
+    /* 0x10002000 serial bus PCI */
+    /* 0x10004000 PL041 audio */
+
+    dev = sysbus_create_varargs("pl181", 0x10005000, pic[9], pic[10], NULL);
+    /* Wire up MMC card detect and read-only signals */
+    qdev_connect_gpio_out(dev, 0,
+                          qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
+    qdev_connect_gpio_out(dev, 1,
+                          qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
+
+    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[12]);
+    sysbus_create_simple("pl050_mouse", 0x10007000, pic[13]);
+
+    sysbus_create_simple("pl011", 0x10009000, pic[5]);
+    sysbus_create_simple("pl011", 0x1000a000, pic[6]);
+    sysbus_create_simple("pl011", 0x1000b000, pic[7]);
+    sysbus_create_simple("pl011", 0x1000c000, pic[8]);
+
+    /* 0x1000f000 SP805 WDT */
+
+    sysbus_create_simple("sp804", 0x10011000, pic[2]);
+    sysbus_create_simple("sp804", 0x10012000, pic[3]);
+
+    /* 0x10016000 Serial Bus DVI */
+
+    sysbus_create_simple("pl031", 0x10017000, pic[4]); /* RTC */
+
+    /* 0x1001a000 Compact Flash */
+
+    /* 0x1001f000 PL111 CLCD (motherboard) */
+
+    /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
+
+    /* 0x10020000 PL111 CLCD (daughterboard) */
+    sysbus_create_simple("pl110", 0x10020000, pic[44]);
+
+    /* 0x10060000 AXI RAM */
+    /* 0x100e0000 PL341 Dynamic Memory Controller */
+    /* 0x100e1000 PL354 Static Memory Controller */
+    /* 0x100e2000 System Configuration Controller */
+
+    sysbus_create_simple("sp804", 0x100e4000, pic[48]);
+    /* 0x100e5000 SP805 Watchdog module */
+    /* 0x100e6000 BP147 TrustZone Protection Controller */
+    /* 0x100e9000 PL301 'Fast' AXI matrix */
+    /* 0x100ea000 PL301 'Slow' AXI matrix */
+    /* 0x100ec000 TrustZone Address Space Controller */
+    /* 0x10200000 CoreSight debug APB */
+    /* 0x1e00a000 PL310 L2 Cache Controller */
+
+    /* CS0: NOR0 flash          : 0x40000000 .. 0x44000000 */
+    /* CS4: NOR1 flash          : 0x44000000 .. 0x48000000 */
+    /* CS2: SRAM                : 0x48000000 .. 0x4a000000 */
+    sram_size = 0x2000000;
+    sram_offset = qemu_ram_alloc(NULL, "vexpress.sram", sram_size);
+    cpu_register_physical_memory(0x48000000, sram_size,
+                                 sram_offset | IO_MEM_RAM);
+
+    /* CS3: USB, ethernet, VRAM : 0x4c000000 .. 0x50000000 */
+
+    /* 0x4c000000 Video RAM */
+    vram_size = 0x800000;
+    vram_offset = qemu_ram_alloc(NULL, "vexpress.vram", vram_size);
+    cpu_register_physical_memory(0x4c000000, vram_size,
+                                 vram_offset | IO_MEM_RAM);
+
+    /* 0x4e000000 LAN9118 Ethernet */
+    if (nd_table[0].vlan) {
+        lan9118_init(&nd_table[0], 0x4e000000, pic[15]);
+    }
+
+    /* 0x4f000000 ISP1761 USB */
+
+    /* ??? Hack to map an additional page of ram for the secondary CPU
+       startup code.  I guess this works on real hardware because the
+       BootROM happens to be in ROM/flash or in memory that isn't clobbered
+       until after Linux boots the secondary CPUs.  */
+    ram_offset = qemu_ram_alloc(NULL, "vexpress.hack", 0x1000);
+    cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
+                                 ram_offset | IO_MEM_RAM);
+
+    vexpress_binfo.ram_size = ram_size;
+    vexpress_binfo.kernel_filename = kernel_filename;
+    vexpress_binfo.kernel_cmdline = kernel_cmdline;
+    vexpress_binfo.initrd_filename = initrd_filename;
+    vexpress_binfo.nb_cpus = smp_cpus;
+    vexpress_binfo.board_id = VEXPRESS_BOARD_ID;
+    vexpress_binfo.loader_start = 0x60000000;
+    arm_load_kernel(first_cpu, &vexpress_binfo);
+}
+
+
+static QEMUMachine vexpress_a9_machine = {
+    .name = "vexpress-a9",
+    .desc = "ARM Versatile Express for Cortex-A9",
+    .init = vexpress_a9_init,
+    .use_scsi = 1,
+    .max_cpus = 4,
+};
+
+static void vexpress_machine_init(void)
+{
+    qemu_register_machine(&vexpress_a9_machine);
+}
+
+machine_init(vexpress_machine_init);
-- 
1.7.1

[Qemu-devel] Re: [PATCH v3 1/2] hw/arm_sysctl.c: Add the Versatile Express system registers

[Juan Quintela]

Peter Maydell <peter.maydell@linaro.org> wrote:
> Add support for the Versatile Express SYS_CFG registers, which provide
> a generic means of reading or writing configuration information from
> various parts of the board. We only implement shutdown and reset.
>
> Also make the RESETCTL register RAZ/WI on Versatile Express rather
> than reset the board. Other system registers are generally the same
> as Versatile and Realview.
>
> This includes a VMState version number bump for arm_sysctl,
> since we have new register state to preserve. It also adds
> sys_mci to the VMState while we're bumping the version number
> (an accidental omission from commit b50ff6f5).

vmstate change ok with me.

Later, Juan.

Re: [Qemu-devel] [PATCH v3 1/2] hw/arm_sysctl.c: Add the Versatile Express system registers

[Aurelien Jarno]

On Mon, Mar 07, 2011 at 11:10:31AM +0000, Peter Maydell wrote:
> Add support for the Versatile Express SYS_CFG registers, which provide
> a generic means of reading or writing configuration information from
> various parts of the board. We only implement shutdown and reset.
> 
> Also make the RESETCTL register RAZ/WI on Versatile Express rather
> than reset the board. Other system registers are generally the same
> as Versatile and Realview.
> 
> This includes a VMState version number bump for arm_sysctl,
> since we have new register state to preserve. It also adds
> sys_mci to the VMState while we're bumping the version number
> (an accidental omission from commit b50ff6f5).
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  hw/arm_sysctl.c |   64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
>  1 files changed, 63 insertions(+), 1 deletions(-)

Thanks, applied.

> diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
> index 799b007..b1110b4 100644
> --- a/hw/arm_sysctl.c
> +++ b/hw/arm_sysctl.c
> @@ -27,11 +27,14 @@ typedef struct {
>      uint32_t resetlevel;
>      uint32_t proc_id;
>      uint32_t sys_mci;
> +    uint32_t sys_cfgdata;
> +    uint32_t sys_cfgctrl;
> +    uint32_t sys_cfgstat;
>  } arm_sysctl_state;
>  
>  static const VMStateDescription vmstate_arm_sysctl = {
>      .name = "realview_sysctl",
> -    .version_id = 1,
> +    .version_id = 2,
>      .minimum_version_id = 1,
>      .fields = (VMStateField[]) {
>          VMSTATE_UINT32(leds, arm_sysctl_state),
> @@ -41,6 +44,10 @@ static const VMStateDescription vmstate_arm_sysctl = {
>          VMSTATE_UINT32(flags, arm_sysctl_state),
>          VMSTATE_UINT32(nvflags, arm_sysctl_state),
>          VMSTATE_UINT32(resetlevel, arm_sysctl_state),
> +        VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
> +        VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
> +        VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
> +        VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
>          VMSTATE_END_OF_LIST()
>      }
>  };
> @@ -53,6 +60,7 @@ static const VMStateDescription vmstate_arm_sysctl = {
>  #define BOARD_ID_EB 0x140
>  #define BOARD_ID_PBA8 0x178
>  #define BOARD_ID_PBX 0x182
> +#define BOARD_ID_VEXPRESS 0x190
>  
>  static int board_id(arm_sysctl_state *s)
>  {
> @@ -104,6 +112,10 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
>      case 0x38: /* NVFLAGS */
>          return s->nvflags;
>      case 0x40: /* RESETCTL */
> +        if (board_id(s) == BOARD_ID_VEXPRESS) {
> +            /* reserved: RAZ/WI */
> +            return 0;
> +        }
>          return s->resetlevel;
>      case 0x44: /* PCICTL */
>          return 1;
> @@ -142,7 +154,23 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
>      case 0xcc: /* SYS_TEST_OSC3 */
>      case 0xd0: /* SYS_TEST_OSC4 */
>          return 0;
> +    case 0xa0: /* SYS_CFGDATA */
> +        if (board_id(s) != BOARD_ID_VEXPRESS) {
> +            goto bad_reg;
> +        }
> +        return s->sys_cfgdata;
> +    case 0xa4: /* SYS_CFGCTRL */
> +        if (board_id(s) != BOARD_ID_VEXPRESS) {
> +            goto bad_reg;
> +        }
> +        return s->sys_cfgctrl;
> +    case 0xa8: /* SYS_CFGSTAT */
> +        if (board_id(s) != BOARD_ID_VEXPRESS) {
> +            goto bad_reg;
> +        }
> +        return s->sys_cfgstat;
>      default:
> +    bad_reg:
>          printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
>          return 0;
>      }
> @@ -190,6 +218,10 @@ static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
>          s->nvflags &= ~val;
>          break;
>      case 0x40: /* RESETCTL */
> +        if (board_id(s) == BOARD_ID_VEXPRESS) {
> +            /* reserved: RAZ/WI */
> +            break;
> +        }
>          if (s->lockval == LOCK_VALUE) {
>              s->resetlevel = val;
>              if (val & 0x100)
> @@ -216,7 +248,37 @@ static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
>      case 0x98: /* OSCRESET3 */
>      case 0x9c: /* OSCRESET4 */
>          break;
> +    case 0xa0: /* SYS_CFGDATA */
> +        if (board_id(s) != BOARD_ID_VEXPRESS) {
> +            goto bad_reg;
> +        }
> +        s->sys_cfgdata = val;
> +        return;
> +    case 0xa4: /* SYS_CFGCTRL */
> +        if (board_id(s) != BOARD_ID_VEXPRESS) {
> +            goto bad_reg;
> +        }
> +        s->sys_cfgctrl = val & ~(3 << 18);
> +        s->sys_cfgstat = 1;            /* complete */
> +        switch (s->sys_cfgctrl) {
> +        case 0xc0800000:            /* SYS_CFG_SHUTDOWN to motherboard */
> +            qemu_system_shutdown_request();
> +            break;
> +        case 0xc0900000:            /* SYS_CFG_REBOOT to motherboard */
> +            qemu_system_reset_request();
> +            break;
> +        default:
> +            s->sys_cfgstat |= 2;        /* error */
> +        }
> +        return;
> +    case 0xa8: /* SYS_CFGSTAT */
> +        if (board_id(s) != BOARD_ID_VEXPRESS) {
> +            goto bad_reg;
> +        }
> +        s->sys_cfgstat = val & 3;
> +        return;
>      default:
> +    bad_reg:
>          printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
>          return;
>      }
> -- 
> 1.7.1
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH v3 2/2] hw/vexpress.c: Add model of ARM Versatile Express board

[Aurelien Jarno]

On Mon, Mar 07, 2011 at 11:10:32AM +0000, Peter Maydell wrote:
> Add a model of the ARM Versatile Express board (with A9MPx4
> daughterboard).
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  Makefile.target |    1 +
>  hw/vexpress.c   |  224 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 225 insertions(+), 0 deletions(-)
>  create mode 100644 hw/vexpress.c
> 
> diff --git a/Makefile.target b/Makefile.target
> index 220589e..949bd4e 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -315,6 +315,7 @@ obj-arm-y += framebuffer.o
>  obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
>  obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
>  obj-arm-y += syborg_virtio.o
> +obj-arm-y += vexpress.o
>  
>  obj-sh4-y = shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
>  obj-sh4-y += sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o
> diff --git a/hw/vexpress.c b/hw/vexpress.c
> new file mode 100644
> index 0000000..9ffd332
> --- /dev/null
> +++ b/hw/vexpress.c
> @@ -0,0 +1,224 @@
> +/*
> + * ARM Versatile Express emulation.
> + *
> + * Copyright (c) 2010 - 2011 B Labs Ltd.
> + * Copyright (c) 2011 Linaro Limited
> + * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
> + *
> + *  This program is free software; you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License version 2 as
> + *  published by the Free Software Foundation.
> + *
> + *  This program is distributed in the hope that it will be useful,
> + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *  GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License along
> + *  with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "sysbus.h"
> +#include "arm-misc.h"
> +#include "primecell.h"
> +#include "devices.h"
> +#include "net.h"
> +#include "sysemu.h"
> +#include "boards.h"
> +
> +#define SMP_BOOT_ADDR 0xe0000000
> +
> +#define VEXPRESS_BOARD_ID 0x8e0
> +
> +static struct arm_boot_info vexpress_binfo = {
> +    .smp_loader_start = SMP_BOOT_ADDR,
> +};
> +
> +static void vexpress_a9_init(ram_addr_t ram_size,
> +                     const char *boot_device,
> +                     const char *kernel_filename, const char *kernel_cmdline,
> +                     const char *initrd_filename, const char *cpu_model)
> +{
> +    CPUState *env = NULL;
> +    ram_addr_t ram_offset, vram_offset, sram_offset;
> +    DeviceState *dev, *sysctl;
> +    SysBusDevice *busdev;
> +    qemu_irq *irqp;
> +    qemu_irq pic[64];
> +    int n;
> +    qemu_irq cpu_irq[4];
> +    uint32_t proc_id;
> +    uint32_t sys_id;
> +    ram_addr_t low_ram_size, vram_size, sram_size;
> +
> +    if (!cpu_model) {
> +        cpu_model = "cortex-a9";
> +    }
> +
> +    for (n = 0; n < smp_cpus; n++) {
> +        env = cpu_init(cpu_model);
> +        if (!env) {
> +            fprintf(stderr, "Unable to find CPU definition\n");
> +            exit(1);
> +        }
> +        irqp = arm_pic_init_cpu(env);
> +        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
> +    }
> +
> +    if (ram_size > 0x40000000) {
> +        /* 1GB is the maximum the address space permits */
> +        fprintf(stderr, "vexpress: cannot model more than 1GB RAM\n");
> +        exit(1);
> +    }
> +
> +    ram_offset = qemu_ram_alloc(NULL, "vexpress.highmem", ram_size);
> +    low_ram_size = ram_size;
> +    if (low_ram_size > 0x4000000) {
> +        low_ram_size = 0x4000000;
> +    }
> +    /* RAM is from 0x60000000 upwards. The bottom 64MB of the
> +     * address space should in theory be remappable to various
> +     * things including ROM or RAM; we always map the RAM there.
> +     */
> +    cpu_register_physical_memory(0x0, low_ram_size, ram_offset | IO_MEM_RAM);
> +    cpu_register_physical_memory(0x60000000, ram_size,
> +                                 ram_offset | IO_MEM_RAM);
> +
> +    /* 0x1e000000 A9MPCore (SCU) private memory region */
> +    dev = qdev_create(NULL, "a9mpcore_priv");
> +    qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
> +    qdev_init_nofail(dev);
> +    busdev = sysbus_from_qdev(dev);
> +    vexpress_binfo.smp_priv_base = 0x1e000000;
> +    sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base);
> +    for (n = 0; n < smp_cpus; n++) {
> +        sysbus_connect_irq(busdev, n, cpu_irq[n]);
> +    }
> +    /* Interrupts [42:0] are from the motherboard;
> +     * [47:43] are reserved; [63:48] are daughterboard
> +     * peripherals. Note that some documentation numbers
> +     * external interrupts starting from 32 (because the
> +     * A9MP has internal interrupts 0..31).
> +     */
> +    for (n = 0; n < 64; n++) {
> +        pic[n] = qdev_get_gpio_in(dev, n);
> +    }
> +
> +    /* Motherboard peripherals CS7 : 0x10000000 .. 0x10020000 */
> +    sys_id = 0x1190f500;
> +    proc_id = 0x0c000191;
> +
> +    /* 0x10000000 System registers */
> +    sysctl = qdev_create(NULL, "realview_sysctl");
> +    qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
> +    qdev_init_nofail(sysctl);
> +    qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
> +    sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
> +
> +    /* 0x10001000 SP810 system control */
> +    /* 0x10002000 serial bus PCI */
> +    /* 0x10004000 PL041 audio */
> +
> +    dev = sysbus_create_varargs("pl181", 0x10005000, pic[9], pic[10], NULL);
> +    /* Wire up MMC card detect and read-only signals */
> +    qdev_connect_gpio_out(dev, 0,
> +                          qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
> +    qdev_connect_gpio_out(dev, 1,
> +                          qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
> +
> +    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[12]);
> +    sysbus_create_simple("pl050_mouse", 0x10007000, pic[13]);
> +
> +    sysbus_create_simple("pl011", 0x10009000, pic[5]);
> +    sysbus_create_simple("pl011", 0x1000a000, pic[6]);
> +    sysbus_create_simple("pl011", 0x1000b000, pic[7]);
> +    sysbus_create_simple("pl011", 0x1000c000, pic[8]);
> +
> +    /* 0x1000f000 SP805 WDT */
> +
> +    sysbus_create_simple("sp804", 0x10011000, pic[2]);
> +    sysbus_create_simple("sp804", 0x10012000, pic[3]);
> +
> +    /* 0x10016000 Serial Bus DVI */
> +
> +    sysbus_create_simple("pl031", 0x10017000, pic[4]); /* RTC */
> +
> +    /* 0x1001a000 Compact Flash */
> +
> +    /* 0x1001f000 PL111 CLCD (motherboard) */
> +
> +    /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
> +
> +    /* 0x10020000 PL111 CLCD (daughterboard) */
> +    sysbus_create_simple("pl110", 0x10020000, pic[44]);
> +
> +    /* 0x10060000 AXI RAM */
> +    /* 0x100e0000 PL341 Dynamic Memory Controller */
> +    /* 0x100e1000 PL354 Static Memory Controller */
> +    /* 0x100e2000 System Configuration Controller */
> +
> +    sysbus_create_simple("sp804", 0x100e4000, pic[48]);
> +    /* 0x100e5000 SP805 Watchdog module */
> +    /* 0x100e6000 BP147 TrustZone Protection Controller */
> +    /* 0x100e9000 PL301 'Fast' AXI matrix */
> +    /* 0x100ea000 PL301 'Slow' AXI matrix */
> +    /* 0x100ec000 TrustZone Address Space Controller */
> +    /* 0x10200000 CoreSight debug APB */
> +    /* 0x1e00a000 PL310 L2 Cache Controller */
> +
> +    /* CS0: NOR0 flash          : 0x40000000 .. 0x44000000 */
> +    /* CS4: NOR1 flash          : 0x44000000 .. 0x48000000 */
> +    /* CS2: SRAM                : 0x48000000 .. 0x4a000000 */
> +    sram_size = 0x2000000;
> +    sram_offset = qemu_ram_alloc(NULL, "vexpress.sram", sram_size);
> +    cpu_register_physical_memory(0x48000000, sram_size,
> +                                 sram_offset | IO_MEM_RAM);
> +
> +    /* CS3: USB, ethernet, VRAM : 0x4c000000 .. 0x50000000 */
> +
> +    /* 0x4c000000 Video RAM */
> +    vram_size = 0x800000;
> +    vram_offset = qemu_ram_alloc(NULL, "vexpress.vram", vram_size);
> +    cpu_register_physical_memory(0x4c000000, vram_size,
> +                                 vram_offset | IO_MEM_RAM);
> +
> +    /* 0x4e000000 LAN9118 Ethernet */
> +    if (nd_table[0].vlan) {
> +        lan9118_init(&nd_table[0], 0x4e000000, pic[15]);
> +    }

It basically means we silently ignore all other network cards the user
asked. Shouldn't we but a warning/error in that case? 

For having the possibility to add more than one card, I guess it's
possible to simulated the PCI controller? Well if the board has any PCI
controller.

Otherwise the patch looks fine to me, it's very nice being able to boot
an ARM board with more than 256MB of RAM.

> +
> +    /* 0x4f000000 ISP1761 USB */
> +
> +    /* ??? Hack to map an additional page of ram for the secondary CPU
> +       startup code.  I guess this works on real hardware because the
> +       BootROM happens to be in ROM/flash or in memory that isn't clobbered
> +       until after Linux boots the secondary CPUs.  */
> +    ram_offset = qemu_ram_alloc(NULL, "vexpress.hack", 0x1000);
> +    cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
> +                                 ram_offset | IO_MEM_RAM);
> +
> +    vexpress_binfo.ram_size = ram_size;
> +    vexpress_binfo.kernel_filename = kernel_filename;
> +    vexpress_binfo.kernel_cmdline = kernel_cmdline;
> +    vexpress_binfo.initrd_filename = initrd_filename;
> +    vexpress_binfo.nb_cpus = smp_cpus;
> +    vexpress_binfo.board_id = VEXPRESS_BOARD_ID;
> +    vexpress_binfo.loader_start = 0x60000000;
> +    arm_load_kernel(first_cpu, &vexpress_binfo);
> +}
> +
> +
> +static QEMUMachine vexpress_a9_machine = {
> +    .name = "vexpress-a9",
> +    .desc = "ARM Versatile Express for Cortex-A9",
> +    .init = vexpress_a9_init,
> +    .use_scsi = 1,
> +    .max_cpus = 4,
> +};
> +
> +static void vexpress_machine_init(void)
> +{
> +    qemu_register_machine(&vexpress_a9_machine);
> +}
> +
> +machine_init(vexpress_machine_init);
> -- 
> 1.7.1
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH v3 2/2] hw/vexpress.c: Add model of ARM Versatile Express board

[Peter Maydell]

On 21 March 2011 20:41, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Mon, Mar 07, 2011 at 11:10:32AM +0000, Peter Maydell wrote:
>> +    /* 0x4e000000 LAN9118 Ethernet */
>> +    if (nd_table[0].vlan) {
>> +        lan9118_init(&nd_table[0], 0x4e000000, pic[15]);
>> +    }
>
> It basically means we silently ignore all other network cards the user
> asked. Shouldn't we but a warning/error in that case?

Well, if you ask for one network card that's the wrong kind
you get an error:
qemu-system-arm: qemu: Unsupported NIC model: ne2k_pci

but you're right that if you ask for several cards we ignore
the other ones.

I just copied this code pattern from hw/integratorcp.c ; if you
want to suggest a better code fragment I'm happy to revise
the patch.
(hw/versatilepb.c is even worse, if I'm reading the code right
it creates rtl8139 cards regardless of what model you ask for...)

Conceptually, though, it seems to me that the right place to
put "the user specified a network card/a USB device/whatever
but nothing in the board model used it" checks is in the
generic code. Otherwise even boards with no network support
at all need to have boilerplate "reject any network card
specification" code, for instance, all boards without USB need
code to reject attempts to define USB devices, and so on...

> For having the possibility to add more than one card, I guess it's
> possible to simulated the PCI controller? Well if the board has any PCI
> controller.

Sadly PCI is not supported by the A9MPx4 daughterboard.

> Otherwise the patch looks fine to me, it's very nice being able to boot
> an ARM board with more than 256MB of RAM.

PS: PBX-A9 also supports 1GB RAM :-) (but for different reasons
doesn't have PCI support and also the model is decidedly inaccurate).

-- PMM

Re: [Qemu-devel] [PATCH v3 2/2] hw/vexpress.c: Add model of ARM Versatile Express board

[Aurelien Jarno]

On Mon, Mar 21, 2011 at 09:19:56PM +0000, Peter Maydell wrote:
> On 21 March 2011 20:41, Aurelien Jarno <aurelien@aurel32.net> wrote:
> > On Mon, Mar 07, 2011 at 11:10:32AM +0000, Peter Maydell wrote:
> >> +    /* 0x4e000000 LAN9118 Ethernet */
> >> +    if (nd_table[0].vlan) {
> >> +        lan9118_init(&nd_table[0], 0x4e000000, pic[15]);
> >> +    }
> >
> > It basically means we silently ignore all other network cards the user
> > asked. Shouldn't we but a warning/error in that case?
> 
> Well, if you ask for one network card that's the wrong kind
> you get an error:
> qemu-system-arm: qemu: Unsupported NIC model: ne2k_pci

Which looks fine.

> but you're right that if you ask for several cards we ignore
> the other ones.
> 
> I just copied this code pattern from hw/integratorcp.c ; if you
> want to suggest a better code fragment I'm happy to revise
> the patch.

Something like that maybe:

if (nb_nics > 1) {
    fprintf(stderr, "Only one network card supported\n");
    exit(1);
}

> (hw/versatilepb.c is even worse, if I'm reading the code right
> it creates rtl8139 cards regardless of what model you ask for...)

IIRC it's because versatilepb doesn't support PCI I/O ports, so this is
the only network card working. In this kind of situations, a comment
would clearly help, also I agree it should simply fail if the user
requested another network card.

> Conceptually, though, it seems to me that the right place to
> put "the user specified a network card/a USB device/whatever
> but nothing in the board model used it" checks is in the
> generic code. Otherwise even boards with no network support
> at all need to have boilerplate "reject any network card
> specification" code, for instance, all boards without USB need
> code to reject attempts to define USB devices, and so on...

I agree that it the long term we should have a better infrastructure for
that. Looks like a bit similar to the maximum memory patch you posted.
Maybe it should be merged in something providing the architectural
limits of an emulated machine (number of CPU also comes to my mind).

> > For having the possibility to add more than one card, I guess it's
> > possible to simulated the PCI controller? Well if the board has any PCI
> > controller.
> 
> Sadly PCI is not supported by the A9MPx4 daughterboard.

:(

> > Otherwise the patch looks fine to me, it's very nice being able to boot
> > an ARM board with more than 256MB of RAM.
> 
> PS: PBX-A9 also supports 1GB RAM :-) (but for different reasons
> doesn't have PCI support and also the model is decidedly inaccurate).
> 

If a distribution wants to choose between providing PBX-A9 and VExpress
kernels, what would you advice?

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH v3 2/2] hw/vexpress.c: Add model of ARM Versatile Express board

[Peter Maydell]

On 22 March 2011 05:50, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Mon, Mar 21, 2011 at 09:19:56PM +0000, Peter Maydell wrote:
>> (hw/versatilepb.c is even worse, if I'm reading the code right
>> it creates rtl8139 cards regardless of what model you ask for...)
>
> IIRC it's because versatilepb doesn't support PCI I/O ports, so this is
> the only network card working.

Actually VersatilePB hardware supports PCI I/O just fine.
I've tested a SATA card and had PCI memory, I/O, interrupts
and DMA working on a PB926. The problems are:
(1) The Linux versatile PCI code is badly broken; Arnd
Bergmann wrote patches to fix this last year but I don't
think they ever got merged upstream
(2) The QEMU versatile PCI model has been written and
tested against the broken Linux code, so (a) issues like this
one with I/O and (b) if you use the fixed Linux code it
doesn't work on the qemu models...

-- PMM

Re: [Qemu-devel] [PATCH v3 2/2] hw/vexpress.c: Add model of ARM Versatile Express board

[Aurelien Jarno]

On Mon, Mar 07, 2011 at 11:10:32AM +0000, Peter Maydell wrote:
> Add a model of the ARM Versatile Express board (with A9MPx4
> daughterboard).
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  Makefile.target |    1 +
>  hw/vexpress.c   |  224 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 225 insertions(+), 0 deletions(-)
>  create mode 100644 hw/vexpress.c

Thanks, applied.

> diff --git a/Makefile.target b/Makefile.target
> index 220589e..949bd4e 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -315,6 +315,7 @@ obj-arm-y += framebuffer.o
>  obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
>  obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
>  obj-arm-y += syborg_virtio.o
> +obj-arm-y += vexpress.o
>  
>  obj-sh4-y = shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
>  obj-sh4-y += sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o
> diff --git a/hw/vexpress.c b/hw/vexpress.c
> new file mode 100644
> index 0000000..9ffd332
> --- /dev/null
> +++ b/hw/vexpress.c
> @@ -0,0 +1,224 @@
> +/*
> + * ARM Versatile Express emulation.
> + *
> + * Copyright (c) 2010 - 2011 B Labs Ltd.
> + * Copyright (c) 2011 Linaro Limited
> + * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
> + *
> + *  This program is free software; you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License version 2 as
> + *  published by the Free Software Foundation.
> + *
> + *  This program is distributed in the hope that it will be useful,
> + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *  GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License along
> + *  with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "sysbus.h"
> +#include "arm-misc.h"
> +#include "primecell.h"
> +#include "devices.h"
> +#include "net.h"
> +#include "sysemu.h"
> +#include "boards.h"
> +
> +#define SMP_BOOT_ADDR 0xe0000000
> +
> +#define VEXPRESS_BOARD_ID 0x8e0
> +
> +static struct arm_boot_info vexpress_binfo = {
> +    .smp_loader_start = SMP_BOOT_ADDR,
> +};
> +
> +static void vexpress_a9_init(ram_addr_t ram_size,
> +                     const char *boot_device,
> +                     const char *kernel_filename, const char *kernel_cmdline,
> +                     const char *initrd_filename, const char *cpu_model)
> +{
> +    CPUState *env = NULL;
> +    ram_addr_t ram_offset, vram_offset, sram_offset;
> +    DeviceState *dev, *sysctl;
> +    SysBusDevice *busdev;
> +    qemu_irq *irqp;
> +    qemu_irq pic[64];
> +    int n;
> +    qemu_irq cpu_irq[4];
> +    uint32_t proc_id;
> +    uint32_t sys_id;
> +    ram_addr_t low_ram_size, vram_size, sram_size;
> +
> +    if (!cpu_model) {
> +        cpu_model = "cortex-a9";
> +    }
> +
> +    for (n = 0; n < smp_cpus; n++) {
> +        env = cpu_init(cpu_model);
> +        if (!env) {
> +            fprintf(stderr, "Unable to find CPU definition\n");
> +            exit(1);
> +        }
> +        irqp = arm_pic_init_cpu(env);
> +        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
> +    }
> +
> +    if (ram_size > 0x40000000) {
> +        /* 1GB is the maximum the address space permits */
> +        fprintf(stderr, "vexpress: cannot model more than 1GB RAM\n");
> +        exit(1);
> +    }
> +
> +    ram_offset = qemu_ram_alloc(NULL, "vexpress.highmem", ram_size);
> +    low_ram_size = ram_size;
> +    if (low_ram_size > 0x4000000) {
> +        low_ram_size = 0x4000000;
> +    }
> +    /* RAM is from 0x60000000 upwards. The bottom 64MB of the
> +     * address space should in theory be remappable to various
> +     * things including ROM or RAM; we always map the RAM there.
> +     */
> +    cpu_register_physical_memory(0x0, low_ram_size, ram_offset | IO_MEM_RAM);
> +    cpu_register_physical_memory(0x60000000, ram_size,
> +                                 ram_offset | IO_MEM_RAM);
> +
> +    /* 0x1e000000 A9MPCore (SCU) private memory region */
> +    dev = qdev_create(NULL, "a9mpcore_priv");
> +    qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
> +    qdev_init_nofail(dev);
> +    busdev = sysbus_from_qdev(dev);
> +    vexpress_binfo.smp_priv_base = 0x1e000000;
> +    sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base);
> +    for (n = 0; n < smp_cpus; n++) {
> +        sysbus_connect_irq(busdev, n, cpu_irq[n]);
> +    }
> +    /* Interrupts [42:0] are from the motherboard;
> +     * [47:43] are reserved; [63:48] are daughterboard
> +     * peripherals. Note that some documentation numbers
> +     * external interrupts starting from 32 (because the
> +     * A9MP has internal interrupts 0..31).
> +     */
> +    for (n = 0; n < 64; n++) {
> +        pic[n] = qdev_get_gpio_in(dev, n);
> +    }
> +
> +    /* Motherboard peripherals CS7 : 0x10000000 .. 0x10020000 */
> +    sys_id = 0x1190f500;
> +    proc_id = 0x0c000191;
> +
> +    /* 0x10000000 System registers */
> +    sysctl = qdev_create(NULL, "realview_sysctl");
> +    qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
> +    qdev_init_nofail(sysctl);
> +    qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
> +    sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
> +
> +    /* 0x10001000 SP810 system control */
> +    /* 0x10002000 serial bus PCI */
> +    /* 0x10004000 PL041 audio */
> +
> +    dev = sysbus_create_varargs("pl181", 0x10005000, pic[9], pic[10], NULL);
> +    /* Wire up MMC card detect and read-only signals */
> +    qdev_connect_gpio_out(dev, 0,
> +                          qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
> +    qdev_connect_gpio_out(dev, 1,
> +                          qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
> +
> +    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[12]);
> +    sysbus_create_simple("pl050_mouse", 0x10007000, pic[13]);
> +
> +    sysbus_create_simple("pl011", 0x10009000, pic[5]);
> +    sysbus_create_simple("pl011", 0x1000a000, pic[6]);
> +    sysbus_create_simple("pl011", 0x1000b000, pic[7]);
> +    sysbus_create_simple("pl011", 0x1000c000, pic[8]);
> +
> +    /* 0x1000f000 SP805 WDT */
> +
> +    sysbus_create_simple("sp804", 0x10011000, pic[2]);
> +    sysbus_create_simple("sp804", 0x10012000, pic[3]);
> +
> +    /* 0x10016000 Serial Bus DVI */
> +
> +    sysbus_create_simple("pl031", 0x10017000, pic[4]); /* RTC */
> +
> +    /* 0x1001a000 Compact Flash */
> +
> +    /* 0x1001f000 PL111 CLCD (motherboard) */
> +
> +    /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
> +
> +    /* 0x10020000 PL111 CLCD (daughterboard) */
> +    sysbus_create_simple("pl110", 0x10020000, pic[44]);
> +
> +    /* 0x10060000 AXI RAM */
> +    /* 0x100e0000 PL341 Dynamic Memory Controller */
> +    /* 0x100e1000 PL354 Static Memory Controller */
> +    /* 0x100e2000 System Configuration Controller */
> +
> +    sysbus_create_simple("sp804", 0x100e4000, pic[48]);
> +    /* 0x100e5000 SP805 Watchdog module */
> +    /* 0x100e6000 BP147 TrustZone Protection Controller */
> +    /* 0x100e9000 PL301 'Fast' AXI matrix */
> +    /* 0x100ea000 PL301 'Slow' AXI matrix */
> +    /* 0x100ec000 TrustZone Address Space Controller */
> +    /* 0x10200000 CoreSight debug APB */
> +    /* 0x1e00a000 PL310 L2 Cache Controller */
> +
> +    /* CS0: NOR0 flash          : 0x40000000 .. 0x44000000 */
> +    /* CS4: NOR1 flash          : 0x44000000 .. 0x48000000 */
> +    /* CS2: SRAM                : 0x48000000 .. 0x4a000000 */
> +    sram_size = 0x2000000;
> +    sram_offset = qemu_ram_alloc(NULL, "vexpress.sram", sram_size);
> +    cpu_register_physical_memory(0x48000000, sram_size,
> +                                 sram_offset | IO_MEM_RAM);
> +
> +    /* CS3: USB, ethernet, VRAM : 0x4c000000 .. 0x50000000 */
> +
> +    /* 0x4c000000 Video RAM */
> +    vram_size = 0x800000;
> +    vram_offset = qemu_ram_alloc(NULL, "vexpress.vram", vram_size);
> +    cpu_register_physical_memory(0x4c000000, vram_size,
> +                                 vram_offset | IO_MEM_RAM);
> +
> +    /* 0x4e000000 LAN9118 Ethernet */
> +    if (nd_table[0].vlan) {
> +        lan9118_init(&nd_table[0], 0x4e000000, pic[15]);
> +    }
> +
> +    /* 0x4f000000 ISP1761 USB */
> +
> +    /* ??? Hack to map an additional page of ram for the secondary CPU
> +       startup code.  I guess this works on real hardware because the
> +       BootROM happens to be in ROM/flash or in memory that isn't clobbered
> +       until after Linux boots the secondary CPUs.  */
> +    ram_offset = qemu_ram_alloc(NULL, "vexpress.hack", 0x1000);
> +    cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
> +                                 ram_offset | IO_MEM_RAM);
> +
> +    vexpress_binfo.ram_size = ram_size;
> +    vexpress_binfo.kernel_filename = kernel_filename;
> +    vexpress_binfo.kernel_cmdline = kernel_cmdline;
> +    vexpress_binfo.initrd_filename = initrd_filename;
> +    vexpress_binfo.nb_cpus = smp_cpus;
> +    vexpress_binfo.board_id = VEXPRESS_BOARD_ID;
> +    vexpress_binfo.loader_start = 0x60000000;
> +    arm_load_kernel(first_cpu, &vexpress_binfo);
> +}
> +
> +
> +static QEMUMachine vexpress_a9_machine = {
> +    .name = "vexpress-a9",
> +    .desc = "ARM Versatile Express for Cortex-A9",
> +    .init = vexpress_a9_init,
> +    .use_scsi = 1,
> +    .max_cpus = 4,
> +};
> +
> +static void vexpress_machine_init(void)
> +{
> +    qemu_register_machine(&vexpress_a9_machine);
> +}
> +
> +machine_init(vexpress_machine_init);
> -- 
> 1.7.1
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net