[Qemu-devel] [PATCH] lm32: rename raise opcode to scall

[Qemu-devel] [PATCH] lm32: rename raise opcode to scall

[Michael Walle]

To be consistent with the new reference manual.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 target-lm32/lm32-decode.h |    2 +-
 target-lm32/translate.c   |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target-lm32/lm32-decode.h b/target-lm32/lm32-decode.h
index f745b39..42205d9 100644
--- a/target-lm32/lm32-decode.h
+++ b/target-lm32/lm32-decode.h
@@ -60,7 +60,7 @@
 #define DEC_NOR     {B8(00000001), B8(00011111)}
 #define DEC_OR      {B8(00001110), B8(00011111)}
 #define DEC_ORHI    {B8(00011110), B8(00111111)}
-#define DEC_RAISE   {B8(00101011), B8(00111111)}
+#define DEC_SCALL   {B8(00101011), B8(00111111)}
 #define DEC_RCSR    {B8(00100100), B8(00111111)}
 #define DEC_SB      {B8(00001100), B8(00111111)}
 #define DEC_SEXTB   {B8(00101100), B8(00111111)}
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 0b0e405..aa08a14 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -583,7 +583,7 @@ static void dec_orhi(DisasContext *dc)
     tcg_gen_ori_tl(cpu_R[dc->r1], cpu_R[dc->r0], (dc->imm16 << 16));
 }
 
-static void dec_raise(DisasContext *dc)
+static void dec_scall(DisasContext *dc)
 {
     TCGv t0;
     int l1;
@@ -1002,7 +1002,7 @@ static const DecoderInfo decinfo[] = {
     {DEC_NOR, dec_nor},
     {DEC_OR, dec_or},
     {DEC_ORHI, dec_orhi},
-    {DEC_RAISE, dec_raise},
+    {DEC_SCALL, dec_scall},
     {DEC_RCSR, dec_rcsr},
     {DEC_SB, dec_sb},
     {DEC_SEXTB, dec_sextb},
-- 
1.7.2.3

[Qemu-devel] Re: [PATCH] lm32: rename raise opcode to scall

[Edgar E. Iglesias]

On Mon, Mar 07, 2011 at 11:00:13PM +0100, Michael Walle wrote:
> To be consistent with the new reference manual.

Applied this and the decoding table patch. Thanks.

Cheers