Re: [PATCH v5 00/11] riscv: Add support for MIPS P8700 CPU

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

Hi,

On 3/7/25 12:49, Djordje Todorovic wrote:
> In v5 of this patch set I addressed two comments:
>    - 02/11: Moved cpu_set_exception_base from target/riscv/translate.c
>    to target/riscv/cpu.c, and added some NULL pointer checking so the
>    code follows the convention
>    - 08/11: Improved git commit message by explaining cmgcr and cpc,
>    and introduced a macro for 0x100 offset used in those features
> 
> The reset of the patches are the same.
> 
> Djordje Todorovic (11):
>    hw/intc: Allow gaps in hartids for aclint and aplic
>    target/riscv: Add cpu_set_exception_base
>    target/riscv: Add MIPS P8700 CPU
>    target/riscv: Add MIPS P8700 CSRs
>    target/riscv: Add mips.ccmov instruction
>    target/riscv: Add mips.pref instruction
>    target/riscv: Add Xmipslsp instructions
>    hw/misc: Add RISC-V CMGCR and CPC device implementations
>    hw/riscv: Add support for MIPS Boston-aia board model
>    hw/pci: Allow explicit function numbers in pci
>    riscv/boston-aia: Add an e1000e NIC in slot 0 func 1

At a glance, various new files miss their SPDX-License-Identifier,
which is now required.

Regards,

Phil.