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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45627898725sm10671255e9.1.2025.07.15.02.59.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Jul 2025 02:59:00 -0700 (PDT) Message-ID: <12b159a9-15b4-456f-a601-feda1176f3f8@linaro.org> Date: Tue, 15 Jul 2025 11:58:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 00/11] riscv: Add support for MIPS P8700 CPU To: Djordje Todorovic , "qemu-devel@nongnu.org" Cc: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" References: <20250703104925.112688-1-djordje.todorovic@htecgroup.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250703104925.112688-1-djordje.todorovic@htecgroup.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 3/7/25 12:49, Djordje Todorovic wrote: > In v5 of this patch set I addressed two comments: > - 02/11: Moved cpu_set_exception_base from target/riscv/translate.c > to target/riscv/cpu.c, and added some NULL pointer checking so the > code follows the convention > - 08/11: Improved git commit message by explaining cmgcr and cpc, > and introduced a macro for 0x100 offset used in those features > > The reset of the patches are the same. > > Djordje Todorovic (11): > hw/intc: Allow gaps in hartids for aclint and aplic > target/riscv: Add cpu_set_exception_base > target/riscv: Add MIPS P8700 CPU > target/riscv: Add MIPS P8700 CSRs > target/riscv: Add mips.ccmov instruction > target/riscv: Add mips.pref instruction > target/riscv: Add Xmipslsp instructions > hw/misc: Add RISC-V CMGCR and CPC device implementations > hw/riscv: Add support for MIPS Boston-aia board model > hw/pci: Allow explicit function numbers in pci > riscv/boston-aia: Add an e1000e NIC in slot 0 func 1 At a glance, various new files miss their SPDX-License-Identifier, which is now required. Regards, Phil.