From: Richard Henderson <richard.henderson@linaro.org>
To: Rajnesh Kanwal <rkanwal@rivosinc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, bin.meng@windriver.com,
liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com,
apatel@ventanamicro.com, beeman@rivosinc.com,
tech-control-transfer-records@lists.riscv.org,
jason.chien@sifive.com, frank.chang@sifive.com
Subject: Re: [PATCH v3 0/6] target/riscv: Add support for Control Transfer Records Ext.
Date: Tue, 5 Nov 2024 10:58:30 +0000 [thread overview]
Message-ID: <12e5b415-a80a-49b3-b98a-33a398ebf56d@linaro.org> (raw)
In-Reply-To: <20241104-b4-ctr_upstream_v3-v3-0-32fd3c48205f@rivosinc.com>
On 11/4/24 21:51, Rajnesh Kanwal wrote:
> target/riscv/cpu.c | 26 ++-
> target/riscv/cpu.h | 13 ++
> target/riscv/cpu_bits.h | 94 ++++++++
> target/riscv/cpu_cfg.h | 2 +
> target/riscv/cpu_helper.c | 266 ++++++++++++++++++++++
> target/riscv/csr.c | 294 ++++++++++++++++++++++++-
> target/riscv/helper.h | 9 +-
> target/riscv/insn32.decode | 2 +-
> target/riscv/insn_trans/trans_privileged.c.inc | 22 +-
> target/riscv/insn_trans/trans_rvi.c.inc | 31 +++
> target/riscv/insn_trans/trans_rvzce.c.inc | 20 ++
> target/riscv/op_helper.c | 155 ++++++++++++-
> target/riscv/tcg/tcg-cpu.c | 11 +
> target/riscv/translate.c | 10 +
> 14 files changed, 941 insertions(+), 14 deletions(-)
You're missing code in machine.c to migrate the new state.
r~
next prev parent reply other threads:[~2024-11-05 10:59 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-04 21:51 [PATCH v3 0/6] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
2024-11-04 21:51 ` [PATCH v3 1/6] target/riscv: Remove obsolete sfence.vm instruction Rajnesh Kanwal
2024-11-04 21:51 ` [PATCH v3 2/6] target/riscv: Add Control Transfer Records CSR definitions Rajnesh Kanwal
2024-11-04 21:51 ` [PATCH v3 3/6] target/riscv: Add support for Control Transfer Records extension CSRs Rajnesh Kanwal
2024-11-04 21:51 ` [PATCH v3 4/6] target/riscv: Add support to record CTR entries Rajnesh Kanwal
2024-11-05 10:50 ` Richard Henderson
2024-11-04 21:51 ` [PATCH v3 5/6] target/riscv: Add CTR sctrclr instruction Rajnesh Kanwal
2024-11-04 21:51 ` [PATCH v3 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs Rajnesh Kanwal
2024-11-05 10:58 ` Richard Henderson [this message]
2024-12-04 12:59 ` [PATCH v3 0/6] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
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