* [Qemu-devel] [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct
@ 2011-03-28 13:44 Peter Maydell
2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 1/5] Allow boards to specify maximum RAM size Peter Maydell
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Peter Maydell @ 2011-03-28 13:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, patches
This fairly simple patchset adds a new 'max_ram' field to the QEMUMachine
structure so that a board model can specify the maximum RAM it will accept.
We can then produce a friendly diagnostic message when the user tries to
start qemu with a '-m' option asking for more RAM than that. (Currently
most of the ARM devboard models respond with an obscure guest crash when
the guest tries to access RAM and finds device registers instead.)
If no maximum size is specified we default to the old behaviour of
"do not impose any limit".
The advantage of doing this in vl.c rather than in each board (apart
from avoiding code duplication) is that we can distinguish between
"the user asked for more RAM than we support" (an error) and "the global
default RAM size is more than our maximum" (just cap the RAM size to
the board maximum).
Changes in v2:
* use target_physaddr_t rather than ram_addr_t for max_ram, so
we can specify maximum ram sizes for 64 bit target boards
* new patches 3,4 which update sun4m to use the generic max_ram, so
we can delete the sun4m-specific code which was doing the same job
* patch 5 does some tidy-up of sun4m init functions; not strictly
related but the assert() at least is enabled by the cleanup done
in patch 3.
The number of changed lines in sun4m.c is a bit alarming but it's
almost all just moving code around...
Peter Maydell (5):
Allow boards to specify maximum RAM size
hw: Add maximum RAM specifications for ARM devboard models
hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs
hw/sun4m: Use the QEMUMachine max_ram to implement memory limit
hw/sun4m: Use a macro to hide the repetitive board init functions
hw/boards.h | 1 +
hw/integratorcp.c | 1 +
hw/realview.c | 11 +
hw/sun4m.c | 586 ++++++++++++++++++++++-------------------------------
hw/versatilepb.c | 5 +
vl.c | 16 ++-
6 files changed, 273 insertions(+), 347 deletions(-)
^ permalink raw reply [flat|nested] 11+ messages in thread* [Qemu-devel] [PATCH v2 1/5] Allow boards to specify maximum RAM size 2011-03-28 13:44 [Qemu-devel] [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct Peter Maydell @ 2011-03-28 13:44 ` Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 2/5] hw: Add maximum RAM specifications for ARM devboard models Peter Maydell ` (4 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Peter Maydell @ 2011-03-28 13:44 UTC (permalink / raw) To: qemu-devel; +Cc: Blue Swirl, patches Allow boards to specify their maximum RAM size in the QEMUMachine struct. This allows us to provide a useful diagnostic if the user tries to specify a RAM size that the board cannot support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/boards.h | 1 + vl.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 1 deletions(-) diff --git a/hw/boards.h b/hw/boards.h index 6f0f0d7..5f41fce 100644 --- a/hw/boards.h +++ b/hw/boards.h @@ -19,6 +19,7 @@ typedef struct QEMUMachine { QEMUMachineInitFunc *init; int use_scsi; int max_cpus; + target_phys_addr_t max_ram; unsigned int no_serial:1, no_parallel:1, use_virtcon:1, diff --git a/vl.c b/vl.c index 192a240..69cb29b 100644 --- a/vl.c +++ b/vl.c @@ -166,6 +166,9 @@ int main(int argc, char **argv) //#define DEBUG_NET //#define DEBUG_SLIRP +/* Note that this default RAM size is capped to any maximum + * RAM size specified in the board's QEMUMachine struct. + */ #define DEFAULT_RAM_SIZE 128 #define MAX_VIRTIO_CONSOLES 1 @@ -3046,8 +3049,19 @@ int main(int argc, char **argv, char **envp) exit(1); /* init the memory */ - if (ram_size == 0) + if (ram_size == 0) { ram_size = DEFAULT_RAM_SIZE * 1024 * 1024; + if (machine->max_ram) { + ram_size = MIN(ram_size, machine->max_ram); + } + } else if (machine->max_ram && ram_size > machine->max_ram) { + /* Since you can only specify ram_size on the command line in MB it's + * OK to round down when printing the machine's maximum. + */ + fprintf(stderr, "qemu: maximum permitted RAM size for '%s' is %ldM\n", + machine->name, (ram_addr_t)(machine->max_ram / (1024 * 1024))); + exit(1); + } /* init the dynamic translator */ cpu_exec_init_all(tb_size * 1024 * 1024); -- 1.7.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 2/5] hw: Add maximum RAM specifications for ARM devboard models 2011-03-28 13:44 [Qemu-devel] [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 1/5] Allow boards to specify maximum RAM size Peter Maydell @ 2011-03-28 13:44 ` Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs Peter Maydell ` (3 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Peter Maydell @ 2011-03-28 13:44 UTC (permalink / raw) To: qemu-devel; +Cc: Blue Swirl, patches Specify the maximum memory permitted for the various ARM devboard models (integratorcp, realview-eb, realview-eb-mpcore, realview-pb-a8, realview-pbx-a9, versatilepb, versatileab). This means we now handle attempts to specify too much RAM gracefully rather than causing the guest to crash in an obscure fashion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/integratorcp.c | 1 + hw/realview.c | 11 +++++++++++ hw/versatilepb.c | 5 +++++ 3 files changed, 17 insertions(+), 0 deletions(-) diff --git a/hw/integratorcp.c b/hw/integratorcp.c index b049940..ccc44db 100644 --- a/hw/integratorcp.c +++ b/hw/integratorcp.c @@ -516,6 +516,7 @@ static QEMUMachine integratorcp_machine = { .name = "integratorcp", .desc = "ARM Integrator/CP (ARM926EJ-S)", .init = integratorcp_init, + .max_ram = 256 * 1024 * 1024, .is_default = 1, }; diff --git a/hw/realview.c b/hw/realview.c index a67861e..a158ade 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -432,6 +432,7 @@ static QEMUMachine realview_eb_machine = { .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", .init = realview_eb_init, .use_scsi = 1, + .max_ram = 256 * 1024 * 1024, }; static QEMUMachine realview_eb_mpcore_machine = { @@ -440,12 +441,18 @@ static QEMUMachine realview_eb_mpcore_machine = { .init = realview_eb_mpcore_init, .use_scsi = 1, .max_cpus = 4, + .max_ram = 256 * 1024 * 1024, }; static QEMUMachine realview_pb_a8_machine = { .name = "realview-pb-a8", .desc = "ARM RealView Platform Baseboard for Cortex-A8", .init = realview_pb_a8_init, + /* The PB-A8 has 512MB; qemu also supports an extra PBX-A9-like + * 512MB although strictly speaking that area of the address + * space is 'reserved' on the PB-A8. + */ + .max_ram = 1024 * 1024 * 1024, }; static QEMUMachine realview_pbx_a9_machine = { @@ -454,6 +461,10 @@ static QEMUMachine realview_pbx_a9_machine = { .init = realview_pbx_a9_init, .use_scsi = 1, .max_cpus = 4, + /* Realview PBX has 1GB of RAM (512MB on the motherboard + * and another 512MB on the daughterboard) + */ + .max_ram = 1024 * 1024 * 1024, }; static void realview_machine_init(void) diff --git a/hw/versatilepb.c b/hw/versatilepb.c index 9f1bfcf..aeddd28 100644 --- a/hw/versatilepb.c +++ b/hw/versatilepb.c @@ -329,6 +329,10 @@ static QEMUMachine versatilepb_machine = { .desc = "ARM Versatile/PB (ARM926EJ-S)", .init = vpb_init, .use_scsi = 1, + /* Hardware allows for up to 512MB expansion memory in two + * non-contiguous sections, but we only support up to 256MB + */ + .max_ram = 256 * 1024 * 1024, }; static QEMUMachine versatileab_machine = { @@ -336,6 +340,7 @@ static QEMUMachine versatileab_machine = { .desc = "ARM Versatile/AB (ARM926EJ-S)", .init = vab_init, .use_scsi = 1, + .max_ram = 256 * 1024 * 1024, }; static void versatile_machine_init(void) -- 1.7.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs 2011-03-28 13:44 [Qemu-devel] [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 1/5] Allow boards to specify maximum RAM size Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 2/5] hw: Add maximum RAM specifications for ARM devboard models Peter Maydell @ 2011-03-28 13:44 ` Peter Maydell 2011-03-28 17:31 ` [Qemu-devel] " Blue Swirl 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 4/5] hw/sun4m: Use the QEMUMachine max_ram to implement memory limit Peter Maydell ` (2 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: Peter Maydell @ 2011-03-28 13:44 UTC (permalink / raw) To: qemu-devel; +Cc: Blue Swirl, patches Combine the per-machine QEMUMachine struct into the per-machine sun4*_hwdef struct. This requires some moving around of init functions to avoid forward references. We also have to move the 'const' attribute from the whole sun4*_hwdef[] array to the individual fields of the structure, because QEMUMachine is not const. The motivation is to allow the init functions to get at the QEMUMachine struct for the board, so we can use its max_ram field rather than having a max_mem field in the sun4*_hwdef struct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/sun4m.c | 596 ++++++++++++++++++++++++++++++------------------------------ 1 files changed, 297 insertions(+), 299 deletions(-) diff --git a/hw/sun4m.c b/hw/sun4m.c index df3aa32..db90fbe 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -87,51 +87,55 @@ #define ESCC_CLOCK 4915200 struct sun4m_hwdef { - target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; - target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; - target_phys_addr_t serial_base, fd_base; - target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base; - target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; - target_phys_addr_t bpp_base, dbri_base, sx_base; - struct { + QEMUMachine machine; + const target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len; + const target_phys_addr_t slavio_base; + const target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; + const target_phys_addr_t serial_base, fd_base; + const target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base; + const target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; + const target_phys_addr_t bpp_base, dbri_base, sx_base; + const struct { target_phys_addr_t reg_base, vram_base; } vsimm[MAX_VSIMMS]; - target_phys_addr_t ecc_base; - uint32_t ecc_version; - uint8_t nvram_machine_id; - uint16_t machine_id; - uint32_t iommu_version; - uint64_t max_mem; + const target_phys_addr_t ecc_base; + const uint32_t ecc_version; + const uint8_t nvram_machine_id; + const uint16_t machine_id; + const uint32_t iommu_version; + const uint64_t max_mem; const char * const default_cpu_model; }; #define MAX_IOUNITS 5 struct sun4d_hwdef { - target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; - target_phys_addr_t counter_base, nvram_base, ms_kb_base; - target_phys_addr_t serial_base; - target_phys_addr_t espdma_base, esp_base; - target_phys_addr_t ledma_base, le_base; - target_phys_addr_t tcx_base; - target_phys_addr_t sbi_base; - uint8_t nvram_machine_id; - uint16_t machine_id; - uint32_t iounit_version; - uint64_t max_mem; + QEMUMachine machine; + const target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; + const target_phys_addr_t counter_base, nvram_base, ms_kb_base; + const target_phys_addr_t serial_base; + const target_phys_addr_t espdma_base, esp_base; + const target_phys_addr_t ledma_base, le_base; + const target_phys_addr_t tcx_base; + const target_phys_addr_t sbi_base; + const uint8_t nvram_machine_id; + const uint16_t machine_id; + const uint32_t iounit_version; + const uint64_t max_mem; const char * const default_cpu_model; }; struct sun4c_hwdef { - target_phys_addr_t iommu_base, slavio_base; - target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; - target_phys_addr_t serial_base, fd_base; - target_phys_addr_t idreg_base, dma_base, esp_base, le_base; - target_phys_addr_t tcx_base, aux1_base; - uint8_t nvram_machine_id; - uint16_t machine_id; - uint32_t iommu_version; - uint64_t max_mem; + QEMUMachine machine; + const target_phys_addr_t iommu_base, slavio_base; + const target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; + const target_phys_addr_t serial_base, fd_base; + const target_phys_addr_t idreg_base, dma_base, esp_base, le_base; + const target_phys_addr_t tcx_base, aux1_base; + const uint8_t nvram_machine_id; + const uint16_t machine_id; + const uint32_t iommu_version; + const uint64_t max_mem; const char * const default_cpu_model; }; @@ -1006,9 +1010,109 @@ enum { ss2000_id, }; -static const struct sun4m_hwdef sun4m_hwdefs[] = { +static struct sun4m_hwdef sun4m_hwdefs[]; + +/* SPARCstation 5 hardware initialisation */ +static void ss5_init(ram_addr_t RAM_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, + kernel_cmdline, initrd_filename, cpu_model); +} + +/* SPARCstation 10 hardware initialisation */ +static void ss10_init(ram_addr_t RAM_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, + kernel_cmdline, initrd_filename, cpu_model); +} + +/* SPARCserver 600MP hardware initialisation */ +static void ss600mp_init(ram_addr_t RAM_size, + const char *boot_device, + const char *kernel_filename, + const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, + kernel_cmdline, initrd_filename, cpu_model); +} + +/* SPARCstation 20 hardware initialisation */ +static void ss20_init(ram_addr_t RAM_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, + kernel_cmdline, initrd_filename, cpu_model); +} + +/* SPARCstation Voyager hardware initialisation */ +static void vger_init(ram_addr_t RAM_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, + kernel_cmdline, initrd_filename, cpu_model); +} + +/* SPARCstation LX hardware initialisation */ +static void ss_lx_init(ram_addr_t RAM_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, + kernel_cmdline, initrd_filename, cpu_model); +} + +/* SPARCstation 4 hardware initialisation */ +static void ss4_init(ram_addr_t RAM_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, + kernel_cmdline, initrd_filename, cpu_model); +} + +/* SPARCClassic hardware initialisation */ +static void scls_init(ram_addr_t RAM_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, + kernel_cmdline, initrd_filename, cpu_model); +} + +/* SPARCbook hardware initialisation */ +static void sbook_init(ram_addr_t RAM_size, + const char *boot_device, + const char *kernel_filename, const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, + kernel_cmdline, initrd_filename, cpu_model); +} + +static struct sun4m_hwdef sun4m_hwdefs[] = { /* SS-5 */ { + .machine = { + .name = "SS-5", + .desc = "Sun4m platform, SPARCstation 5", + .init = ss5_init, + .use_scsi = 1, + .is_default = 1, + }, .iommu_base = 0x10000000, .iommu_pad_base = 0x10004000, .iommu_pad_len = 0x0fffb000, @@ -1037,6 +1141,13 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }, /* SS-10 */ { + .machine = { + .name = "SS-10", + .desc = "Sun4m platform, SPARCstation 10", + .init = ss10_init, + .use_scsi = 1, + .max_cpus = 4, + }, .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, .slavio_base = 0xff0000000ULL, @@ -1063,6 +1174,13 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }, /* SS-600MP */ { + .machine = { + .name = "SS-600MP", + .desc = "Sun4m platform, SPARCserver 600MP", + .init = ss600mp_init, + .use_scsi = 1, + .max_cpus = 4, + }, .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, .slavio_base = 0xff0000000ULL, @@ -1087,6 +1205,13 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }, /* SS-20 */ { + .machine = { + .name = "SS-20", + .desc = "Sun4m platform, SPARCstation 20", + .init = ss20_init, + .use_scsi = 1, + .max_cpus = 4, + }, .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, .slavio_base = 0xff0000000ULL, @@ -1129,6 +1254,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }, /* Voyager */ { + .machine = { + .name = "Voyager", + .desc = "Sun4m platform, SPARCstation Voyager", + .init = vger_init, + .use_scsi = 1, + }, .iommu_base = 0x10000000, .tcx_base = 0x50000000, .slavio_base = 0x70000000, @@ -1153,6 +1284,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }, /* LX */ { + .machine = { + .name = "LX", + .desc = "Sun4m platform, SPARCstation LX", + .init = ss_lx_init, + .use_scsi = 1, + }, .iommu_base = 0x10000000, .iommu_pad_base = 0x10004000, .iommu_pad_len = 0x0fffb000, @@ -1178,6 +1315,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }, /* SS-4 */ { + .machine = { + .name = "SS-4", + .desc = "Sun4m platform, SPARCstation 4", + .init = ss4_init, + .use_scsi = 1, + }, .iommu_base = 0x10000000, .tcx_base = 0x50000000, .cs_base = 0x6c000000, @@ -1203,6 +1346,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }, /* SPARCClassic */ { + .machine = { + .name = "SPARCClassic", + .desc = "Sun4m platform, SPARCClassic", + .init = scls_init, + .use_scsi = 1, + }, .iommu_base = 0x10000000, .tcx_base = 0x50000000, .slavio_base = 0x70000000, @@ -1227,6 +1376,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }, /* SPARCbook */ { + .machine = { + .name = "SPARCbook", + .desc = "Sun4m platform, SPARCbook", + .init = sbook_init, + .use_scsi = 1, + }, .iommu_base = 0x10000000, .tcx_base = 0x50000000, // XXX .slavio_base = 0x70000000, @@ -1251,219 +1406,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { }, }; -/* SPARCstation 5 hardware initialisation */ -static void ss5_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCstation 10 hardware initialisation */ -static void ss10_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCserver 600MP hardware initialisation */ -static void ss600mp_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, - const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCstation 20 hardware initialisation */ -static void ss20_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCstation Voyager hardware initialisation */ -static void vger_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCstation LX hardware initialisation */ -static void ss_lx_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCstation 4 hardware initialisation */ -static void ss4_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCClassic hardware initialisation */ -static void scls_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCbook hardware initialisation */ -static void sbook_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -static QEMUMachine ss5_machine = { - .name = "SS-5", - .desc = "Sun4m platform, SPARCstation 5", - .init = ss5_init, - .use_scsi = 1, - .is_default = 1, -}; - -static QEMUMachine ss10_machine = { - .name = "SS-10", - .desc = "Sun4m platform, SPARCstation 10", - .init = ss10_init, - .use_scsi = 1, - .max_cpus = 4, -}; - -static QEMUMachine ss600mp_machine = { - .name = "SS-600MP", - .desc = "Sun4m platform, SPARCserver 600MP", - .init = ss600mp_init, - .use_scsi = 1, - .max_cpus = 4, -}; - -static QEMUMachine ss20_machine = { - .name = "SS-20", - .desc = "Sun4m platform, SPARCstation 20", - .init = ss20_init, - .use_scsi = 1, - .max_cpus = 4, -}; - -static QEMUMachine voyager_machine = { - .name = "Voyager", - .desc = "Sun4m platform, SPARCstation Voyager", - .init = vger_init, - .use_scsi = 1, -}; - -static QEMUMachine ss_lx_machine = { - .name = "LX", - .desc = "Sun4m platform, SPARCstation LX", - .init = ss_lx_init, - .use_scsi = 1, -}; - -static QEMUMachine ss4_machine = { - .name = "SS-4", - .desc = "Sun4m platform, SPARCstation 4", - .init = ss4_init, - .use_scsi = 1, -}; - -static QEMUMachine scls_machine = { - .name = "SPARCClassic", - .desc = "Sun4m platform, SPARCClassic", - .init = scls_init, - .use_scsi = 1, -}; - -static QEMUMachine sbook_machine = { - .name = "SPARCbook", - .desc = "Sun4m platform, SPARCbook", - .init = sbook_init, - .use_scsi = 1, -}; - -static const struct sun4d_hwdef sun4d_hwdefs[] = { - /* SS-1000 */ - { - .iounit_bases = { - 0xfe0200000ULL, - 0xfe1200000ULL, - 0xfe2200000ULL, - 0xfe3200000ULL, - -1, - }, - .tcx_base = 0x820000000ULL, - .slavio_base = 0xf00000000ULL, - .ms_kb_base = 0xf00240000ULL, - .serial_base = 0xf00200000ULL, - .nvram_base = 0xf00280000ULL, - .counter_base = 0xf00300000ULL, - .espdma_base = 0x800081000ULL, - .esp_base = 0x800080000ULL, - .ledma_base = 0x800040000ULL, - .le_base = 0x800060000ULL, - .sbi_base = 0xf02800000ULL, - .nvram_machine_id = 0x80, - .machine_id = ss1000_id, - .iounit_version = 0x03000000, - .max_mem = 0xf00000000ULL, - .default_cpu_model = "TI SuperSparc II", - }, - /* SS-2000 */ - { - .iounit_bases = { - 0xfe0200000ULL, - 0xfe1200000ULL, - 0xfe2200000ULL, - 0xfe3200000ULL, - 0xfe4200000ULL, - }, - .tcx_base = 0x820000000ULL, - .slavio_base = 0xf00000000ULL, - .ms_kb_base = 0xf00240000ULL, - .serial_base = 0xf00200000ULL, - .nvram_base = 0xf00280000ULL, - .counter_base = 0xf00300000ULL, - .espdma_base = 0x800081000ULL, - .esp_base = 0x800080000ULL, - .ledma_base = 0x800040000ULL, - .le_base = 0x800060000ULL, - .sbi_base = 0xf02800000ULL, - .nvram_machine_id = 0x80, - .machine_id = ss2000_id, - .iounit_version = 0x03000000, - .max_mem = 0xf00000000ULL, - .default_cpu_model = "TI SuperSparc II", - }, -}; - static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq) { DeviceState *dev; @@ -1599,6 +1541,8 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); } +static struct sun4d_hwdef sun4d_hwdefs[]; + /* SPARCserver 1000 hardware initialisation */ static void ss1000_init(ram_addr_t RAM_size, const char *boot_device, @@ -1619,42 +1563,72 @@ static void ss2000_init(ram_addr_t RAM_size, kernel_cmdline, initrd_filename, cpu_model); } -static QEMUMachine ss1000_machine = { - .name = "SS-1000", - .desc = "Sun4d platform, SPARCserver 1000", - .init = ss1000_init, - .use_scsi = 1, - .max_cpus = 8, -}; - -static QEMUMachine ss2000_machine = { - .name = "SS-2000", - .desc = "Sun4d platform, SPARCcenter 2000", - .init = ss2000_init, - .use_scsi = 1, - .max_cpus = 20, -}; - -static const struct sun4c_hwdef sun4c_hwdefs[] = { - /* SS-2 */ +static struct sun4d_hwdef sun4d_hwdefs[] = { + /* SS-1000 */ { - .iommu_base = 0xf8000000, - .tcx_base = 0xfe000000, - .slavio_base = 0xf6000000, - .intctl_base = 0xf5000000, - .counter_base = 0xf3000000, - .ms_kb_base = 0xf0000000, - .serial_base = 0xf1000000, - .nvram_base = 0xf2000000, - .fd_base = 0xf7200000, - .dma_base = 0xf8400000, - .esp_base = 0xf8800000, - .le_base = 0xf8c00000, - .aux1_base = 0xf7400003, - .nvram_machine_id = 0x55, - .machine_id = ss2_id, - .max_mem = 0x10000000, - .default_cpu_model = "Cypress CY7C601", + .machine = { + .name = "SS-1000", + .desc = "Sun4d platform, SPARCserver 1000", + .init = ss1000_init, + .use_scsi = 1, + .max_cpus = 8, + }, + .iounit_bases = { + 0xfe0200000ULL, + 0xfe1200000ULL, + 0xfe2200000ULL, + 0xfe3200000ULL, + -1, + }, + .tcx_base = 0x820000000ULL, + .slavio_base = 0xf00000000ULL, + .ms_kb_base = 0xf00240000ULL, + .serial_base = 0xf00200000ULL, + .nvram_base = 0xf00280000ULL, + .counter_base = 0xf00300000ULL, + .espdma_base = 0x800081000ULL, + .esp_base = 0x800080000ULL, + .ledma_base = 0x800040000ULL, + .le_base = 0x800060000ULL, + .sbi_base = 0xf02800000ULL, + .nvram_machine_id = 0x80, + .machine_id = ss1000_id, + .iounit_version = 0x03000000, + .max_mem = 0xf00000000ULL, + .default_cpu_model = "TI SuperSparc II", + }, + /* SS-2000 */ + { + .machine = { + .name = "SS-2000", + .desc = "Sun4d platform, SPARCcenter 2000", + .init = ss2000_init, + .use_scsi = 1, + .max_cpus = 20, + }, + .iounit_bases = { + 0xfe0200000ULL, + 0xfe1200000ULL, + 0xfe2200000ULL, + 0xfe3200000ULL, + 0xfe4200000ULL, + }, + .tcx_base = 0x820000000ULL, + .slavio_base = 0xf00000000ULL, + .ms_kb_base = 0xf00240000ULL, + .serial_base = 0xf00200000ULL, + .nvram_base = 0xf00280000ULL, + .counter_base = 0xf00300000ULL, + .espdma_base = 0x800081000ULL, + .esp_base = 0x800080000ULL, + .ledma_base = 0x800040000ULL, + .le_base = 0x800060000ULL, + .sbi_base = 0xf02800000ULL, + .nvram_machine_id = 0x80, + .machine_id = ss2000_id, + .iounit_version = 0x03000000, + .max_mem = 0xf00000000ULL, + .default_cpu_model = "TI SuperSparc II", }, }; @@ -1791,6 +1765,8 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); } +static struct sun4c_hwdef sun4c_hwdefs[]; + /* SPARCstation 2 hardware initialisation */ static void ss2_init(ram_addr_t RAM_size, const char *boot_device, @@ -1801,27 +1777,49 @@ static void ss2_init(ram_addr_t RAM_size, kernel_cmdline, initrd_filename, cpu_model); } -static QEMUMachine ss2_machine = { - .name = "SS-2", - .desc = "Sun4c platform, SPARCstation 2", - .init = ss2_init, - .use_scsi = 1, +static struct sun4c_hwdef sun4c_hwdefs[] = { + /* SS-2 */ + { + .machine = { + .name = "SS-2", + .desc = "Sun4c platform, SPARCstation 2", + .init = ss2_init, + .use_scsi = 1, + }, + .iommu_base = 0xf8000000, + .tcx_base = 0xfe000000, + .slavio_base = 0xf6000000, + .intctl_base = 0xf5000000, + .counter_base = 0xf3000000, + .ms_kb_base = 0xf0000000, + .serial_base = 0xf1000000, + .nvram_base = 0xf2000000, + .fd_base = 0xf7200000, + .dma_base = 0xf8400000, + .esp_base = 0xf8800000, + .le_base = 0xf8c00000, + .aux1_base = 0xf7400003, + .nvram_machine_id = 0x55, + .machine_id = ss2_id, + .max_mem = 0x10000000, + .default_cpu_model = "Cypress CY7C601", + }, }; static void ss2_machine_init(void) { - qemu_register_machine(&ss5_machine); - qemu_register_machine(&ss10_machine); - qemu_register_machine(&ss600mp_machine); - qemu_register_machine(&ss20_machine); - qemu_register_machine(&voyager_machine); - qemu_register_machine(&ss_lx_machine); - qemu_register_machine(&ss4_machine); - qemu_register_machine(&scls_machine); - qemu_register_machine(&sbook_machine); - qemu_register_machine(&ss1000_machine); - qemu_register_machine(&ss2000_machine); - qemu_register_machine(&ss2_machine); + int i; + for (i = 0; i < ARRAY_SIZE(sun4m_hwdefs); i++) { + qemu_register_machine(&sun4m_hwdefs[i].machine); + } + + for (i = 0; i < ARRAY_SIZE(sun4d_hwdefs); i++) { + qemu_register_machine(&sun4d_hwdefs[i].machine); + } + + for (i = 0; i < ARRAY_SIZE(sun4c_hwdefs); i++) { + qemu_register_machine(&sun4c_hwdefs[i].machine); + } } machine_init(ss2_machine_init); -- 1.7.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] Re: [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs Peter Maydell @ 2011-03-28 17:31 ` Blue Swirl 2011-03-28 17:36 ` Peter Maydell 0 siblings, 1 reply; 11+ messages in thread From: Blue Swirl @ 2011-03-28 17:31 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel, patches On Mon, Mar 28, 2011 at 4:44 PM, Peter Maydell <peter.maydell@linaro.org> wrote: > Combine the per-machine QEMUMachine struct into the per-machine > sun4*_hwdef struct. This requires some moving around of init functions > to avoid forward references. We also have to move the 'const' > attribute from the whole sun4*_hwdef[] array to the individual fields > of the structure, because QEMUMachine is not const. Maybe QEMUMachine should be made const instead? The data does not ever need to change. > The motivation is to allow the init functions to get at the > QEMUMachine struct for the board, so we can use its max_ram field > rather than having a max_mem field in the sun4*_hwdef struct. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > hw/sun4m.c | 596 ++++++++++++++++++++++++++++++------------------------------ > 1 files changed, 297 insertions(+), 299 deletions(-) > > diff --git a/hw/sun4m.c b/hw/sun4m.c > index df3aa32..db90fbe 100644 > --- a/hw/sun4m.c > +++ b/hw/sun4m.c > @@ -87,51 +87,55 @@ > #define ESCC_CLOCK 4915200 > > struct sun4m_hwdef { > - target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; > - target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; > - target_phys_addr_t serial_base, fd_base; > - target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base; > - target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; > - target_phys_addr_t bpp_base, dbri_base, sx_base; > - struct { > + QEMUMachine machine; > + const target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len; > + const target_phys_addr_t slavio_base; > + const target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; > + const target_phys_addr_t serial_base, fd_base; > + const target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base; > + const target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; > + const target_phys_addr_t bpp_base, dbri_base, sx_base; > + const struct { > target_phys_addr_t reg_base, vram_base; > } vsimm[MAX_VSIMMS]; > - target_phys_addr_t ecc_base; > - uint32_t ecc_version; > - uint8_t nvram_machine_id; > - uint16_t machine_id; > - uint32_t iommu_version; > - uint64_t max_mem; > + const target_phys_addr_t ecc_base; > + const uint32_t ecc_version; > + const uint8_t nvram_machine_id; > + const uint16_t machine_id; > + const uint32_t iommu_version; > + const uint64_t max_mem; > const char * const default_cpu_model; > }; > > #define MAX_IOUNITS 5 > > struct sun4d_hwdef { > - target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; > - target_phys_addr_t counter_base, nvram_base, ms_kb_base; > - target_phys_addr_t serial_base; > - target_phys_addr_t espdma_base, esp_base; > - target_phys_addr_t ledma_base, le_base; > - target_phys_addr_t tcx_base; > - target_phys_addr_t sbi_base; > - uint8_t nvram_machine_id; > - uint16_t machine_id; > - uint32_t iounit_version; > - uint64_t max_mem; > + QEMUMachine machine; > + const target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; > + const target_phys_addr_t counter_base, nvram_base, ms_kb_base; > + const target_phys_addr_t serial_base; > + const target_phys_addr_t espdma_base, esp_base; > + const target_phys_addr_t ledma_base, le_base; > + const target_phys_addr_t tcx_base; > + const target_phys_addr_t sbi_base; > + const uint8_t nvram_machine_id; > + const uint16_t machine_id; > + const uint32_t iounit_version; > + const uint64_t max_mem; > const char * const default_cpu_model; > }; > > struct sun4c_hwdef { > - target_phys_addr_t iommu_base, slavio_base; > - target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; > - target_phys_addr_t serial_base, fd_base; > - target_phys_addr_t idreg_base, dma_base, esp_base, le_base; > - target_phys_addr_t tcx_base, aux1_base; > - uint8_t nvram_machine_id; > - uint16_t machine_id; > - uint32_t iommu_version; > - uint64_t max_mem; > + QEMUMachine machine; > + const target_phys_addr_t iommu_base, slavio_base; > + const target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; > + const target_phys_addr_t serial_base, fd_base; > + const target_phys_addr_t idreg_base, dma_base, esp_base, le_base; > + const target_phys_addr_t tcx_base, aux1_base; > + const uint8_t nvram_machine_id; > + const uint16_t machine_id; > + const uint32_t iommu_version; > + const uint64_t max_mem; > const char * const default_cpu_model; > }; > > @@ -1006,9 +1010,109 @@ enum { > ss2000_id, > }; > > -static const struct sun4m_hwdef sun4m_hwdefs[] = { > +static struct sun4m_hwdef sun4m_hwdefs[]; > + > +/* SPARCstation 5 hardware initialisation */ > +static void ss5_init(ram_addr_t RAM_size, > + const char *boot_device, > + const char *kernel_filename, const char *kernel_cmdline, > + const char *initrd_filename, const char *cpu_model) > +{ > + sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, > + kernel_cmdline, initrd_filename, cpu_model); > +} > + > +/* SPARCstation 10 hardware initialisation */ > +static void ss10_init(ram_addr_t RAM_size, > + const char *boot_device, > + const char *kernel_filename, const char *kernel_cmdline, > + const char *initrd_filename, const char *cpu_model) > +{ > + sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, > + kernel_cmdline, initrd_filename, cpu_model); > +} > + > +/* SPARCserver 600MP hardware initialisation */ > +static void ss600mp_init(ram_addr_t RAM_size, > + const char *boot_device, > + const char *kernel_filename, > + const char *kernel_cmdline, > + const char *initrd_filename, const char *cpu_model) > +{ > + sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, > + kernel_cmdline, initrd_filename, cpu_model); > +} > + > +/* SPARCstation 20 hardware initialisation */ > +static void ss20_init(ram_addr_t RAM_size, > + const char *boot_device, > + const char *kernel_filename, const char *kernel_cmdline, > + const char *initrd_filename, const char *cpu_model) > +{ > + sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, > + kernel_cmdline, initrd_filename, cpu_model); > +} > + > +/* SPARCstation Voyager hardware initialisation */ > +static void vger_init(ram_addr_t RAM_size, > + const char *boot_device, > + const char *kernel_filename, const char *kernel_cmdline, > + const char *initrd_filename, const char *cpu_model) > +{ > + sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, > + kernel_cmdline, initrd_filename, cpu_model); > +} > + > +/* SPARCstation LX hardware initialisation */ > +static void ss_lx_init(ram_addr_t RAM_size, > + const char *boot_device, > + const char *kernel_filename, const char *kernel_cmdline, > + const char *initrd_filename, const char *cpu_model) > +{ > + sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, > + kernel_cmdline, initrd_filename, cpu_model); > +} > + > +/* SPARCstation 4 hardware initialisation */ > +static void ss4_init(ram_addr_t RAM_size, > + const char *boot_device, > + const char *kernel_filename, const char *kernel_cmdline, > + const char *initrd_filename, const char *cpu_model) > +{ > + sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, > + kernel_cmdline, initrd_filename, cpu_model); > +} > + > +/* SPARCClassic hardware initialisation */ > +static void scls_init(ram_addr_t RAM_size, > + const char *boot_device, > + const char *kernel_filename, const char *kernel_cmdline, > + const char *initrd_filename, const char *cpu_model) > +{ > + sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, > + kernel_cmdline, initrd_filename, cpu_model); > +} > + > +/* SPARCbook hardware initialisation */ > +static void sbook_init(ram_addr_t RAM_size, > + const char *boot_device, > + const char *kernel_filename, const char *kernel_cmdline, > + const char *initrd_filename, const char *cpu_model) > +{ > + sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, > + kernel_cmdline, initrd_filename, cpu_model); > +} > + > +static struct sun4m_hwdef sun4m_hwdefs[] = { > /* SS-5 */ > { > + .machine = { > + .name = "SS-5", > + .desc = "Sun4m platform, SPARCstation 5", > + .init = ss5_init, > + .use_scsi = 1, > + .is_default = 1, > + }, > .iommu_base = 0x10000000, > .iommu_pad_base = 0x10004000, > .iommu_pad_len = 0x0fffb000, > @@ -1037,6 +1141,13 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { > }, > /* SS-10 */ > { > + .machine = { > + .name = "SS-10", > + .desc = "Sun4m platform, SPARCstation 10", > + .init = ss10_init, > + .use_scsi = 1, > + .max_cpus = 4, > + }, > .iommu_base = 0xfe0000000ULL, > .tcx_base = 0xe20000000ULL, > .slavio_base = 0xff0000000ULL, > @@ -1063,6 +1174,13 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { > }, > /* SS-600MP */ > { > + .machine = { > + .name = "SS-600MP", > + .desc = "Sun4m platform, SPARCserver 600MP", > + .init = ss600mp_init, > + .use_scsi = 1, > + .max_cpus = 4, > + }, > .iommu_base = 0xfe0000000ULL, > .tcx_base = 0xe20000000ULL, > .slavio_base = 0xff0000000ULL, > @@ -1087,6 +1205,13 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { > }, > /* SS-20 */ > { > + .machine = { > + .name = "SS-20", > + .desc = "Sun4m platform, SPARCstation 20", > + .init = ss20_init, > + .use_scsi = 1, > + .max_cpus = 4, > + }, > .iommu_base = 0xfe0000000ULL, > .tcx_base = 0xe20000000ULL, > .slavio_base = 0xff0000000ULL, > @@ -1129,6 +1254,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { > }, > /* Voyager */ > { > + .machine = { > + .name = "Voyager", > + .desc = "Sun4m platform, SPARCstation Voyager", > + .init = vger_init, > + .use_scsi = 1, > + }, > .iommu_base = 0x10000000, > .tcx_base = 0x50000000, > .slavio_base = 0x70000000, > @@ -1153,6 +1284,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { > }, > /* LX */ > { > + .machine = { > + .name = "LX", > + .desc = "Sun4m platform, SPARCstation LX", > + .init = ss_lx_init, > + .use_scsi = 1, > + }, > .iommu_base = 0x10000000, > .iommu_pad_base = 0x10004000, > .iommu_pad_len = 0x0fffb000, > @@ -1178,6 +1315,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { > }, > /* SS-4 */ > { > + .machine = { > + .name = "SS-4", > + .desc = "Sun4m platform, SPARCstation 4", > + .init = ss4_init, > + .use_scsi = 1, > + }, > .iommu_base = 0x10000000, > .tcx_base = 0x50000000, > .cs_base = 0x6c000000, > @@ -1203,6 +1346,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { > }, > /* SPARCClassic */ > { > + .machine = { > + .name = "SPARCClassic", > + .desc = "Sun4m platform, SPARCClassic", > + .init = scls_init, > + .use_scsi = 1, > + }, > .iommu_base = 0x10000000, > .tcx_base = 0x50000000, > .slavio_base = 0x70000000, > @@ -1227,6 +1376,12 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { > }, > /* SPARCbook */ > { > + .machine = { > + .name = "SPARCbook", > + .desc = "Sun4m platform, SPARCbook", > + .init = sbook_init, > + .use_scsi = 1, > + }, > .iommu_base = 0x10000000, > .tcx_base = 0x50000000, // XXX > .slavio_base = 0x70000000, > @@ -1251,219 +1406,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = { > }, > }; > > -/* SPARCstation 5 hardware initialisation */ > -static void ss5_init(ram_addr_t RAM_size, > - const char *boot_device, > - const char *kernel_filename, const char *kernel_cmdline, > - const char *initrd_filename, const char *cpu_model) > -{ > - sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, > - kernel_cmdline, initrd_filename, cpu_model); > -} > - > -/* SPARCstation 10 hardware initialisation */ > -static void ss10_init(ram_addr_t RAM_size, > - const char *boot_device, > - const char *kernel_filename, const char *kernel_cmdline, > - const char *initrd_filename, const char *cpu_model) > -{ > - sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, > - kernel_cmdline, initrd_filename, cpu_model); > -} > - > -/* SPARCserver 600MP hardware initialisation */ > -static void ss600mp_init(ram_addr_t RAM_size, > - const char *boot_device, > - const char *kernel_filename, > - const char *kernel_cmdline, > - const char *initrd_filename, const char *cpu_model) > -{ > - sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, > - kernel_cmdline, initrd_filename, cpu_model); > -} > - > -/* SPARCstation 20 hardware initialisation */ > -static void ss20_init(ram_addr_t RAM_size, > - const char *boot_device, > - const char *kernel_filename, const char *kernel_cmdline, > - const char *initrd_filename, const char *cpu_model) > -{ > - sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, > - kernel_cmdline, initrd_filename, cpu_model); > -} > - > -/* SPARCstation Voyager hardware initialisation */ > -static void vger_init(ram_addr_t RAM_size, > - const char *boot_device, > - const char *kernel_filename, const char *kernel_cmdline, > - const char *initrd_filename, const char *cpu_model) > -{ > - sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, > - kernel_cmdline, initrd_filename, cpu_model); > -} > - > -/* SPARCstation LX hardware initialisation */ > -static void ss_lx_init(ram_addr_t RAM_size, > - const char *boot_device, > - const char *kernel_filename, const char *kernel_cmdline, > - const char *initrd_filename, const char *cpu_model) > -{ > - sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, > - kernel_cmdline, initrd_filename, cpu_model); > -} > - > -/* SPARCstation 4 hardware initialisation */ > -static void ss4_init(ram_addr_t RAM_size, > - const char *boot_device, > - const char *kernel_filename, const char *kernel_cmdline, > - const char *initrd_filename, const char *cpu_model) > -{ > - sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, > - kernel_cmdline, initrd_filename, cpu_model); > -} > - > -/* SPARCClassic hardware initialisation */ > -static void scls_init(ram_addr_t RAM_size, > - const char *boot_device, > - const char *kernel_filename, const char *kernel_cmdline, > - const char *initrd_filename, const char *cpu_model) > -{ > - sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, > - kernel_cmdline, initrd_filename, cpu_model); > -} > - > -/* SPARCbook hardware initialisation */ > -static void sbook_init(ram_addr_t RAM_size, > - const char *boot_device, > - const char *kernel_filename, const char *kernel_cmdline, > - const char *initrd_filename, const char *cpu_model) > -{ > - sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, > - kernel_cmdline, initrd_filename, cpu_model); > -} > - > -static QEMUMachine ss5_machine = { > - .name = "SS-5", > - .desc = "Sun4m platform, SPARCstation 5", > - .init = ss5_init, > - .use_scsi = 1, > - .is_default = 1, > -}; > - > -static QEMUMachine ss10_machine = { > - .name = "SS-10", > - .desc = "Sun4m platform, SPARCstation 10", > - .init = ss10_init, > - .use_scsi = 1, > - .max_cpus = 4, > -}; > - > -static QEMUMachine ss600mp_machine = { > - .name = "SS-600MP", > - .desc = "Sun4m platform, SPARCserver 600MP", > - .init = ss600mp_init, > - .use_scsi = 1, > - .max_cpus = 4, > -}; > - > -static QEMUMachine ss20_machine = { > - .name = "SS-20", > - .desc = "Sun4m platform, SPARCstation 20", > - .init = ss20_init, > - .use_scsi = 1, > - .max_cpus = 4, > -}; > - > -static QEMUMachine voyager_machine = { > - .name = "Voyager", > - .desc = "Sun4m platform, SPARCstation Voyager", > - .init = vger_init, > - .use_scsi = 1, > -}; > - > -static QEMUMachine ss_lx_machine = { > - .name = "LX", > - .desc = "Sun4m platform, SPARCstation LX", > - .init = ss_lx_init, > - .use_scsi = 1, > -}; > - > -static QEMUMachine ss4_machine = { > - .name = "SS-4", > - .desc = "Sun4m platform, SPARCstation 4", > - .init = ss4_init, > - .use_scsi = 1, > -}; > - > -static QEMUMachine scls_machine = { > - .name = "SPARCClassic", > - .desc = "Sun4m platform, SPARCClassic", > - .init = scls_init, > - .use_scsi = 1, > -}; > - > -static QEMUMachine sbook_machine = { > - .name = "SPARCbook", > - .desc = "Sun4m platform, SPARCbook", > - .init = sbook_init, > - .use_scsi = 1, > -}; > - > -static const struct sun4d_hwdef sun4d_hwdefs[] = { > - /* SS-1000 */ > - { > - .iounit_bases = { > - 0xfe0200000ULL, > - 0xfe1200000ULL, > - 0xfe2200000ULL, > - 0xfe3200000ULL, > - -1, > - }, > - .tcx_base = 0x820000000ULL, > - .slavio_base = 0xf00000000ULL, > - .ms_kb_base = 0xf00240000ULL, > - .serial_base = 0xf00200000ULL, > - .nvram_base = 0xf00280000ULL, > - .counter_base = 0xf00300000ULL, > - .espdma_base = 0x800081000ULL, > - .esp_base = 0x800080000ULL, > - .ledma_base = 0x800040000ULL, > - .le_base = 0x800060000ULL, > - .sbi_base = 0xf02800000ULL, > - .nvram_machine_id = 0x80, > - .machine_id = ss1000_id, > - .iounit_version = 0x03000000, > - .max_mem = 0xf00000000ULL, > - .default_cpu_model = "TI SuperSparc II", > - }, > - /* SS-2000 */ > - { > - .iounit_bases = { > - 0xfe0200000ULL, > - 0xfe1200000ULL, > - 0xfe2200000ULL, > - 0xfe3200000ULL, > - 0xfe4200000ULL, > - }, > - .tcx_base = 0x820000000ULL, > - .slavio_base = 0xf00000000ULL, > - .ms_kb_base = 0xf00240000ULL, > - .serial_base = 0xf00200000ULL, > - .nvram_base = 0xf00280000ULL, > - .counter_base = 0xf00300000ULL, > - .espdma_base = 0x800081000ULL, > - .esp_base = 0x800080000ULL, > - .ledma_base = 0x800040000ULL, > - .le_base = 0x800060000ULL, > - .sbi_base = 0xf02800000ULL, > - .nvram_machine_id = 0x80, > - .machine_id = ss2000_id, > - .iounit_version = 0x03000000, > - .max_mem = 0xf00000000ULL, > - .default_cpu_model = "TI SuperSparc II", > - }, > -}; > - > static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq) > { > DeviceState *dev; > @@ -1599,6 +1541,8 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, > qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); > } > > +static struct sun4d_hwdef sun4d_hwdefs[]; > + > /* SPARCserver 1000 hardware initialisation */ > static void ss1000_init(ram_addr_t RAM_size, > const char *boot_device, > @@ -1619,42 +1563,72 @@ static void ss2000_init(ram_addr_t RAM_size, > kernel_cmdline, initrd_filename, cpu_model); > } > > -static QEMUMachine ss1000_machine = { > - .name = "SS-1000", > - .desc = "Sun4d platform, SPARCserver 1000", > - .init = ss1000_init, > - .use_scsi = 1, > - .max_cpus = 8, > -}; > - > -static QEMUMachine ss2000_machine = { > - .name = "SS-2000", > - .desc = "Sun4d platform, SPARCcenter 2000", > - .init = ss2000_init, > - .use_scsi = 1, > - .max_cpus = 20, > -}; > - > -static const struct sun4c_hwdef sun4c_hwdefs[] = { > - /* SS-2 */ > +static struct sun4d_hwdef sun4d_hwdefs[] = { > + /* SS-1000 */ > { > - .iommu_base = 0xf8000000, > - .tcx_base = 0xfe000000, > - .slavio_base = 0xf6000000, > - .intctl_base = 0xf5000000, > - .counter_base = 0xf3000000, > - .ms_kb_base = 0xf0000000, > - .serial_base = 0xf1000000, > - .nvram_base = 0xf2000000, > - .fd_base = 0xf7200000, > - .dma_base = 0xf8400000, > - .esp_base = 0xf8800000, > - .le_base = 0xf8c00000, > - .aux1_base = 0xf7400003, > - .nvram_machine_id = 0x55, > - .machine_id = ss2_id, > - .max_mem = 0x10000000, > - .default_cpu_model = "Cypress CY7C601", > + .machine = { > + .name = "SS-1000", > + .desc = "Sun4d platform, SPARCserver 1000", > + .init = ss1000_init, > + .use_scsi = 1, > + .max_cpus = 8, > + }, > + .iounit_bases = { > + 0xfe0200000ULL, > + 0xfe1200000ULL, > + 0xfe2200000ULL, > + 0xfe3200000ULL, > + -1, > + }, > + .tcx_base = 0x820000000ULL, > + .slavio_base = 0xf00000000ULL, > + .ms_kb_base = 0xf00240000ULL, > + .serial_base = 0xf00200000ULL, > + .nvram_base = 0xf00280000ULL, > + .counter_base = 0xf00300000ULL, > + .espdma_base = 0x800081000ULL, > + .esp_base = 0x800080000ULL, > + .ledma_base = 0x800040000ULL, > + .le_base = 0x800060000ULL, > + .sbi_base = 0xf02800000ULL, > + .nvram_machine_id = 0x80, > + .machine_id = ss1000_id, > + .iounit_version = 0x03000000, > + .max_mem = 0xf00000000ULL, > + .default_cpu_model = "TI SuperSparc II", > + }, > + /* SS-2000 */ > + { > + .machine = { > + .name = "SS-2000", > + .desc = "Sun4d platform, SPARCcenter 2000", > + .init = ss2000_init, > + .use_scsi = 1, > + .max_cpus = 20, > + }, > + .iounit_bases = { > + 0xfe0200000ULL, > + 0xfe1200000ULL, > + 0xfe2200000ULL, > + 0xfe3200000ULL, > + 0xfe4200000ULL, > + }, > + .tcx_base = 0x820000000ULL, > + .slavio_base = 0xf00000000ULL, > + .ms_kb_base = 0xf00240000ULL, > + .serial_base = 0xf00200000ULL, > + .nvram_base = 0xf00280000ULL, > + .counter_base = 0xf00300000ULL, > + .espdma_base = 0x800081000ULL, > + .esp_base = 0x800080000ULL, > + .ledma_base = 0x800040000ULL, > + .le_base = 0x800060000ULL, > + .sbi_base = 0xf02800000ULL, > + .nvram_machine_id = 0x80, > + .machine_id = ss2000_id, > + .iounit_version = 0x03000000, > + .max_mem = 0xf00000000ULL, > + .default_cpu_model = "TI SuperSparc II", > }, > }; > > @@ -1791,6 +1765,8 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, > qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); > } > > +static struct sun4c_hwdef sun4c_hwdefs[]; > + > /* SPARCstation 2 hardware initialisation */ > static void ss2_init(ram_addr_t RAM_size, > const char *boot_device, > @@ -1801,27 +1777,49 @@ static void ss2_init(ram_addr_t RAM_size, > kernel_cmdline, initrd_filename, cpu_model); > } > > -static QEMUMachine ss2_machine = { > - .name = "SS-2", > - .desc = "Sun4c platform, SPARCstation 2", > - .init = ss2_init, > - .use_scsi = 1, > +static struct sun4c_hwdef sun4c_hwdefs[] = { > + /* SS-2 */ > + { > + .machine = { > + .name = "SS-2", > + .desc = "Sun4c platform, SPARCstation 2", > + .init = ss2_init, > + .use_scsi = 1, > + }, > + .iommu_base = 0xf8000000, > + .tcx_base = 0xfe000000, > + .slavio_base = 0xf6000000, > + .intctl_base = 0xf5000000, > + .counter_base = 0xf3000000, > + .ms_kb_base = 0xf0000000, > + .serial_base = 0xf1000000, > + .nvram_base = 0xf2000000, > + .fd_base = 0xf7200000, > + .dma_base = 0xf8400000, > + .esp_base = 0xf8800000, > + .le_base = 0xf8c00000, > + .aux1_base = 0xf7400003, > + .nvram_machine_id = 0x55, > + .machine_id = ss2_id, > + .max_mem = 0x10000000, > + .default_cpu_model = "Cypress CY7C601", > + }, > }; > > static void ss2_machine_init(void) > { > - qemu_register_machine(&ss5_machine); > - qemu_register_machine(&ss10_machine); > - qemu_register_machine(&ss600mp_machine); > - qemu_register_machine(&ss20_machine); > - qemu_register_machine(&voyager_machine); > - qemu_register_machine(&ss_lx_machine); > - qemu_register_machine(&ss4_machine); > - qemu_register_machine(&scls_machine); > - qemu_register_machine(&sbook_machine); > - qemu_register_machine(&ss1000_machine); > - qemu_register_machine(&ss2000_machine); > - qemu_register_machine(&ss2_machine); > + int i; > + for (i = 0; i < ARRAY_SIZE(sun4m_hwdefs); i++) { > + qemu_register_machine(&sun4m_hwdefs[i].machine); > + } > + > + for (i = 0; i < ARRAY_SIZE(sun4d_hwdefs); i++) { > + qemu_register_machine(&sun4d_hwdefs[i].machine); > + } > + > + for (i = 0; i < ARRAY_SIZE(sun4c_hwdefs); i++) { > + qemu_register_machine(&sun4c_hwdefs[i].machine); > + } > } > > machine_init(ss2_machine_init); > -- > 1.7.1 > > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] Re: [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs 2011-03-28 17:31 ` [Qemu-devel] " Blue Swirl @ 2011-03-28 17:36 ` Peter Maydell 2011-03-28 17:58 ` Blue Swirl 0 siblings, 1 reply; 11+ messages in thread From: Peter Maydell @ 2011-03-28 17:36 UTC (permalink / raw) To: Blue Swirl; +Cc: qemu-devel, patches On 28 March 2011 18:31, Blue Swirl <blauwirbel@gmail.com> wrote: > On Mon, Mar 28, 2011 at 4:44 PM, Peter Maydell <peter.maydell@linaro.org> wrote: >> Combine the per-machine QEMUMachine struct into the per-machine >> sun4*_hwdef struct. This requires some moving around of init functions >> to avoid forward references. We also have to move the 'const' >> attribute from the whole sun4*_hwdef[] array to the individual fields >> of the structure, because QEMUMachine is not const. > > Maybe QEMUMachine should be made const instead? The data does not ever > need to change. I thought about that, but we need to fill in the 'next' links when we do qemu_register_device(). (vl.c also sets machine->max_cpus if it wasn't set. I don't think anything else modifies QEMUMachine structure fields.) -- PMM ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] Re: [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs 2011-03-28 17:36 ` Peter Maydell @ 2011-03-28 17:58 ` Blue Swirl 2011-03-28 18:05 ` Peter Maydell 0 siblings, 1 reply; 11+ messages in thread From: Blue Swirl @ 2011-03-28 17:58 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel, patches On Mon, Mar 28, 2011 at 8:36 PM, Peter Maydell <peter.maydell@linaro.org> wrote: > On 28 March 2011 18:31, Blue Swirl <blauwirbel@gmail.com> wrote: >> On Mon, Mar 28, 2011 at 4:44 PM, Peter Maydell <peter.maydell@linaro.org> wrote: >>> Combine the per-machine QEMUMachine struct into the per-machine >>> sun4*_hwdef struct. This requires some moving around of init functions >>> to avoid forward references. We also have to move the 'const' >>> attribute from the whole sun4*_hwdef[] array to the individual fields >>> of the structure, because QEMUMachine is not const. >> >> Maybe QEMUMachine should be made const instead? The data does not ever >> need to change. > > I thought about that, but we need to fill in the 'next' links when > we do qemu_register_device(). The list could be kept separate from the structure. > (vl.c also sets machine->max_cpus if it wasn't set. I don't think > anything else modifies QEMUMachine structure fields.) The lines after that could be changed so that machine->max_cpus is not changed. It's not used afterwards. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] Re: [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs 2011-03-28 17:58 ` Blue Swirl @ 2011-03-28 18:05 ` Peter Maydell 0 siblings, 0 replies; 11+ messages in thread From: Peter Maydell @ 2011-03-28 18:05 UTC (permalink / raw) To: Blue Swirl; +Cc: qemu-devel, patches On 28 March 2011 18:58, Blue Swirl <blauwirbel@gmail.com> wrote: > On Mon, Mar 28, 2011 at 8:36 PM, Peter Maydell <peter.maydell@linaro.org> wrote: >> On 28 March 2011 18:31, Blue Swirl <blauwirbel@gmail.com> wrote: >>> On Mon, Mar 28, 2011 at 4:44 PM, Peter Maydell <peter.maydell@linaro.org> wrote: >>>> Combine the per-machine QEMUMachine struct into the per-machine >>>> sun4*_hwdef struct. This requires some moving around of init functions >>>> to avoid forward references. We also have to move the 'const' >>>> attribute from the whole sun4*_hwdef[] array to the individual fields >>>> of the structure, because QEMUMachine is not const. >>> >>> Maybe QEMUMachine should be made const instead? The data does not ever >>> need to change. >> >> I thought about that, but we need to fill in the 'next' links when >> we do qemu_register_device(). > > The list could be kept separate from the structure. Well, we could, but I tend to find separate list headers a bit ugly. -- PMM ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 4/5] hw/sun4m: Use the QEMUMachine max_ram to implement memory limit 2011-03-28 13:44 [Qemu-devel] [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct Peter Maydell ` (2 preceding siblings ...) 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs Peter Maydell @ 2011-03-28 13:44 ` Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 5/5] hw/sun4m: Use a macro to hide the repetitive board init functions Peter Maydell 2011-03-28 17:32 ` [Qemu-devel] Re: [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct Blue Swirl 5 siblings, 0 replies; 11+ messages in thread From: Peter Maydell @ 2011-03-28 13:44 UTC (permalink / raw) To: qemu-devel; +Cc: Blue Swirl, patches Use the max_ram field in QEMUMachine to indicate maximum memory, rather than a field in the sun4*_hwdef structure. This allows us to use the vl.c check on RAM specifications rather than having to code our own. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/sun4m.c | 42 ++++++++++++++++-------------------------- 1 files changed, 16 insertions(+), 26 deletions(-) diff --git a/hw/sun4m.c b/hw/sun4m.c index db90fbe..47692dd 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -103,7 +103,6 @@ struct sun4m_hwdef { const uint8_t nvram_machine_id; const uint16_t machine_id; const uint32_t iommu_version; - const uint64_t max_mem; const char * const default_cpu_model; }; @@ -121,7 +120,6 @@ struct sun4d_hwdef { const uint8_t nvram_machine_id; const uint16_t machine_id; const uint32_t iounit_version; - const uint64_t max_mem; const char * const default_cpu_model; }; @@ -135,7 +133,6 @@ struct sun4c_hwdef { const uint8_t nvram_machine_id; const uint16_t machine_id; const uint32_t iommu_version; - const uint64_t max_mem; const char * const default_cpu_model; }; @@ -747,13 +744,6 @@ static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, RamDevice *d; /* allocate RAM */ - if ((uint64_t)RAM_size > max_mem) { - fprintf(stderr, - "qemu: Too much memory for this machine: %d, maximum %d\n", - (unsigned int)(RAM_size / (1024 * 1024)), - (unsigned int)(max_mem / (1024 * 1024))); - exit(1); - } dev = qdev_create(NULL, "memory"); s = sysbus_from_qdev(dev); @@ -834,10 +824,10 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, /* set up devices */ - ram_init(0, RAM_size, hwdef->max_mem); + ram_init(0, RAM_size, hwdef->machine.max_ram); /* models without ECC don't trap when missing ram is accessed */ if (!hwdef->ecc_base) { - empty_slot_init(RAM_size, hwdef->max_mem - RAM_size); + empty_slot_init(RAM_size, hwdef->machine.max_ram - RAM_size); } prom_init(hwdef->slavio_base, bios_name); @@ -1111,6 +1101,7 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .desc = "Sun4m platform, SPARCstation 5", .init = ss5_init, .use_scsi = 1, + .max_ram = 0x10000000, .is_default = 1, }, .iommu_base = 0x10000000, @@ -1136,7 +1127,6 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = ss5_id, .iommu_version = 0x05000000, - .max_mem = 0x10000000, .default_cpu_model = "Fujitsu MB86904", }, /* SS-10 */ @@ -1147,6 +1137,7 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .init = ss10_init, .use_scsi = 1, .max_cpus = 4, + .max_ram = 0xf00000000ULL, }, .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, @@ -1169,7 +1160,6 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x72, .machine_id = ss10_id, .iommu_version = 0x03000000, - .max_mem = 0xf00000000ULL, .default_cpu_model = "TI SuperSparc II", }, /* SS-600MP */ @@ -1180,6 +1170,7 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .init = ss600mp_init, .use_scsi = 1, .max_cpus = 4, + .max_ram = 0xf00000000ULL, }, .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, @@ -1200,7 +1191,6 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x71, .machine_id = ss600mp_id, .iommu_version = 0x01000000, - .max_mem = 0xf00000000ULL, .default_cpu_model = "TI SuperSparc II", }, /* SS-20 */ @@ -1211,6 +1201,7 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .init = ss20_init, .use_scsi = 1, .max_cpus = 4, + .max_ram = 0xf00000000ULL, }, .iommu_base = 0xfe0000000ULL, .tcx_base = 0xe20000000ULL, @@ -1249,7 +1240,6 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x72, .machine_id = ss20_id, .iommu_version = 0x13000000, - .max_mem = 0xf00000000ULL, .default_cpu_model = "TI SuperSparc II", }, /* Voyager */ @@ -1259,6 +1249,7 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .desc = "Sun4m platform, SPARCstation Voyager", .init = vger_init, .use_scsi = 1, + .max_ram = 0x10000000, }, .iommu_base = 0x10000000, .tcx_base = 0x50000000, @@ -1279,7 +1270,6 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = vger_id, .iommu_version = 0x05000000, - .max_mem = 0x10000000, .default_cpu_model = "Fujitsu MB86904", }, /* LX */ @@ -1289,6 +1279,7 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .desc = "Sun4m platform, SPARCstation LX", .init = ss_lx_init, .use_scsi = 1, + .max_ram = 0x10000000, }, .iommu_base = 0x10000000, .iommu_pad_base = 0x10004000, @@ -1310,7 +1301,6 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = lx_id, .iommu_version = 0x04000000, - .max_mem = 0x10000000, .default_cpu_model = "TI MicroSparc I", }, /* SS-4 */ @@ -1320,6 +1310,7 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .desc = "Sun4m platform, SPARCstation 4", .init = ss4_init, .use_scsi = 1, + .max_ram = 0x10000000, }, .iommu_base = 0x10000000, .tcx_base = 0x50000000, @@ -1341,7 +1332,6 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = ss4_id, .iommu_version = 0x05000000, - .max_mem = 0x10000000, .default_cpu_model = "Fujitsu MB86904", }, /* SPARCClassic */ @@ -1351,6 +1341,7 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .desc = "Sun4m platform, SPARCClassic", .init = scls_init, .use_scsi = 1, + .max_ram = 0x10000000, }, .iommu_base = 0x10000000, .tcx_base = 0x50000000, @@ -1371,7 +1362,6 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = scls_id, .iommu_version = 0x05000000, - .max_mem = 0x10000000, .default_cpu_model = "TI MicroSparc I", }, /* SPARCbook */ @@ -1381,6 +1371,7 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .desc = "Sun4m platform, SPARCbook", .init = sbook_init, .use_scsi = 1, + .max_ram = 0x10000000, }, .iommu_base = 0x10000000, .tcx_base = 0x50000000, // XXX @@ -1401,7 +1392,6 @@ static struct sun4m_hwdef sun4m_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = sbook_id, .iommu_version = 0x05000000, - .max_mem = 0x10000000, .default_cpu_model = "TI MicroSparc I", }, }; @@ -1453,7 +1443,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); /* set up devices */ - ram_init(0, RAM_size, hwdef->max_mem); + ram_init(0, RAM_size, hwdef->machine.max_ram); prom_init(hwdef->slavio_base, bios_name); @@ -1572,6 +1562,7 @@ static struct sun4d_hwdef sun4d_hwdefs[] = { .init = ss1000_init, .use_scsi = 1, .max_cpus = 8, + .max_ram = 0xf00000000ULL, }, .iounit_bases = { 0xfe0200000ULL, @@ -1594,7 +1585,6 @@ static struct sun4d_hwdef sun4d_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = ss1000_id, .iounit_version = 0x03000000, - .max_mem = 0xf00000000ULL, .default_cpu_model = "TI SuperSparc II", }, /* SS-2000 */ @@ -1605,6 +1595,7 @@ static struct sun4d_hwdef sun4d_hwdefs[] = { .init = ss2000_init, .use_scsi = 1, .max_cpus = 20, + .max_ram = 0xf00000000ULL, }, .iounit_bases = { 0xfe0200000ULL, @@ -1627,7 +1618,6 @@ static struct sun4d_hwdef sun4d_hwdefs[] = { .nvram_machine_id = 0x80, .machine_id = ss2000_id, .iounit_version = 0x03000000, - .max_mem = 0xf00000000ULL, .default_cpu_model = "TI SuperSparc II", }, }; @@ -1675,7 +1665,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs); /* set up devices */ - ram_init(0, RAM_size, hwdef->max_mem); + ram_init(0, RAM_size, hwdef->machine.max_ram); prom_init(hwdef->slavio_base, bios_name); @@ -1785,6 +1775,7 @@ static struct sun4c_hwdef sun4c_hwdefs[] = { .desc = "Sun4c platform, SPARCstation 2", .init = ss2_init, .use_scsi = 1, + .max_ram = 0x10000000, }, .iommu_base = 0xf8000000, .tcx_base = 0xfe000000, @@ -1801,7 +1792,6 @@ static struct sun4c_hwdef sun4c_hwdefs[] = { .aux1_base = 0xf7400003, .nvram_machine_id = 0x55, .machine_id = ss2_id, - .max_mem = 0x10000000, .default_cpu_model = "Cypress CY7C601", }, }; -- 1.7.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 5/5] hw/sun4m: Use a macro to hide the repetitive board init functions 2011-03-28 13:44 [Qemu-devel] [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct Peter Maydell ` (3 preceding siblings ...) 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 4/5] hw/sun4m: Use the QEMUMachine max_ram to implement memory limit Peter Maydell @ 2011-03-28 13:44 ` Peter Maydell 2011-03-28 17:32 ` [Qemu-devel] Re: [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct Blue Swirl 5 siblings, 0 replies; 11+ messages in thread From: Peter Maydell @ 2011-03-28 13:44 UTC (permalink / raw) To: qemu-devel; +Cc: Blue Swirl, patches Tidy up the repetitive board init functions (which are all the same apart from which hwdef struct they pass in). This also lets us add an assertion that the hwdef points to the init function which uses that hwdef, rather than some other one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/sun4m.c | 138 ++++++++++-------------------------------------------------- 1 files changed, 22 insertions(+), 116 deletions(-) diff --git a/hw/sun4m.c b/hw/sun4m.c index 47692dd..75155e2 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -1002,96 +1002,27 @@ enum { static struct sun4m_hwdef sun4m_hwdefs[]; -/* SPARCstation 5 hardware initialisation */ -static void ss5_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCstation 10 hardware initialisation */ -static void ss10_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCserver 600MP hardware initialisation */ -static void ss600mp_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, - const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCstation 20 hardware initialisation */ -static void ss20_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCstation Voyager hardware initialisation */ -static void vger_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); +#define SUN4_INITFN(NAME, SUBARCH, OFFSET) \ +static void NAME##_init(ram_addr_t RAM_size, \ + const char *boot_device, \ + const char *kernel_filename, const char *kernel_cmdline, \ + const char *initrd_filename, const char *cpu_model) \ +{ \ + assert(SUBARCH##_hwdefs[OFFSET].machine.init == NAME##_init); \ + SUBARCH##_hw_init(&SUBARCH##_hwdefs[OFFSET], RAM_size, boot_device, \ + kernel_filename, kernel_cmdline, initrd_filename, \ + cpu_model); \ } -/* SPARCstation LX hardware initialisation */ -static void ss_lx_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCstation 4 hardware initialisation */ -static void ss4_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCClassic hardware initialisation */ -static void scls_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCbook hardware initialisation */ -static void sbook_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} +SUN4_INITFN(ss5, sun4m, 0) +SUN4_INITFN(ss10, sun4m, 1) +SUN4_INITFN(ss600mp, sun4m, 2) +SUN4_INITFN(ss20, sun4m, 3) +SUN4_INITFN(vger, sun4m, 4) +SUN4_INITFN(ss_lx, sun4m, 5) +SUN4_INITFN(ss4, sun4m, 6) +SUN4_INITFN(scls, sun4m, 7) +SUN4_INITFN(sbook, sun4m, 8) static struct sun4m_hwdef sun4m_hwdefs[] = { /* SS-5 */ @@ -1533,25 +1464,8 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, static struct sun4d_hwdef sun4d_hwdefs[]; -/* SPARCserver 1000 hardware initialisation */ -static void ss1000_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} - -/* SPARCcenter 2000 hardware initialisation */ -static void ss2000_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} +SUN4_INITFN(ss1000, sun4d, 0) +SUN4_INITFN(ss2000, sun4d, 1) static struct sun4d_hwdef sun4d_hwdefs[] = { /* SS-1000 */ @@ -1757,15 +1671,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, static struct sun4c_hwdef sun4c_hwdefs[]; -/* SPARCstation 2 hardware initialisation */ -static void ss2_init(ram_addr_t RAM_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model) -{ - sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); -} +SUN4_INITFN(ss2, sun4c, 0) static struct sun4c_hwdef sun4c_hwdefs[] = { /* SS-2 */ -- 1.7.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] Re: [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct 2011-03-28 13:44 [Qemu-devel] [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct Peter Maydell ` (4 preceding siblings ...) 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 5/5] hw/sun4m: Use a macro to hide the repetitive board init functions Peter Maydell @ 2011-03-28 17:32 ` Blue Swirl 5 siblings, 0 replies; 11+ messages in thread From: Blue Swirl @ 2011-03-28 17:32 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel, patches On Mon, Mar 28, 2011 at 4:44 PM, Peter Maydell <peter.maydell@linaro.org> wrote: > This fairly simple patchset adds a new 'max_ram' field to the QEMUMachine > structure so that a board model can specify the maximum RAM it will accept. > We can then produce a friendly diagnostic message when the user tries to > start qemu with a '-m' option asking for more RAM than that. (Currently > most of the ARM devboard models respond with an obscure guest crash when > the guest tries to access RAM and finds device registers instead.) > > If no maximum size is specified we default to the old behaviour of > "do not impose any limit". > > The advantage of doing this in vl.c rather than in each board (apart > from avoiding code duplication) is that we can distinguish between > "the user asked for more RAM than we support" (an error) and "the global > default RAM size is more than our maximum" (just cap the RAM size to > the board maximum). > > Changes in v2: > * use target_physaddr_t rather than ram_addr_t for max_ram, so > we can specify maximum ram sizes for 64 bit target boards > * new patches 3,4 which update sun4m to use the generic max_ram, so > we can delete the sun4m-specific code which was doing the same job > * patch 5 does some tidy-up of sun4m init functions; not strictly > related but the assert() at least is enabled by the cleanup done > in patch 3. > > The number of changed lines in sun4m.c is a bit alarming but it's > almost all just moving code around... Very nice patch set! ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2011-03-28 18:05 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-03-28 13:44 [Qemu-devel] [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 1/5] Allow boards to specify maximum RAM size Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 2/5] hw: Add maximum RAM specifications for ARM devboard models Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 3/5] hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs Peter Maydell 2011-03-28 17:31 ` [Qemu-devel] " Blue Swirl 2011-03-28 17:36 ` Peter Maydell 2011-03-28 17:58 ` Blue Swirl 2011-03-28 18:05 ` Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 4/5] hw/sun4m: Use the QEMUMachine max_ram to implement memory limit Peter Maydell 2011-03-28 13:44 ` [Qemu-devel] [PATCH v2 5/5] hw/sun4m: Use a macro to hide the repetitive board init functions Peter Maydell 2011-03-28 17:32 ` [Qemu-devel] Re: [PATCH v2 0/5] Let boards state maximum RAM limits in QEMUMachine struct Blue Swirl
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