From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=57207 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Q5fNJ-0002m6-U7 for qemu-devel@nongnu.org; Fri, 01 Apr 2011 10:30:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Q5fNI-0004tK-MZ for qemu-devel@nongnu.org; Fri, 01 Apr 2011 10:30:57 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:45963) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Q5fNI-0004or-BM for qemu-devel@nongnu.org; Fri, 01 Apr 2011 10:30:56 -0400 From: Peter Maydell Date: Fri, 1 Apr 2011 15:30:37 +0100 Message-Id: <1301668243-29886-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1301668243-29886-1-git-send-email-peter.maydell@linaro.org> References: <1301668243-29886-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 04/10] target-arm: Fix VCLE.F32 #0, VCLT.F32 #0 NaN handling List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori , qemu-devel@nongnu.org Cc: Aurelien Jarno Implementing the floating-point versions of VCLE #0 and VCLT #0 by doing a GT comparison and inverting the result gives the wrong result if the input is a NaN. Implement as a GT comparison with the operands swapped instead. Signed-off-by: Peter Maydell --- target-arm/translate.c | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index cf2440e..6ce8b7a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5641,25 +5641,31 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) gen_neon_rsb(size, tmp, tmp2); tcg_temp_free(tmp2); break; - case 24: case 27: /* Float VCGT #0, Float VCLE #0 */ + case 24: /* Float VCGT #0 */ tmp2 = tcg_const_i32(0); gen_helper_neon_cgt_f32(tmp, cpu_env, tmp, tmp2); tcg_temp_free(tmp2); - if (op == 27) - tcg_gen_not_i32(tmp, tmp); break; - case 25: case 28: /* Float VCGE #0, Float VCLT #0 */ + case 25: /* Float VCGE #0 */ tmp2 = tcg_const_i32(0); gen_helper_neon_cge_f32(tmp, cpu_env, tmp, tmp2); tcg_temp_free(tmp2); - if (op == 28) - tcg_gen_not_i32(tmp, tmp); break; case 26: /* Float VCEQ #0 */ tmp2 = tcg_const_i32(0); gen_helper_neon_ceq_f32(tmp, cpu_env, tmp, tmp2); tcg_temp_free(tmp2); break; + case 27: /* Float VCLE #0 */ + tmp2 = tcg_const_i32(0); + gen_helper_neon_cge_f32(tmp, cpu_env, tmp2, tmp); + tcg_temp_free(tmp2); + break; + case 28: /* Float VCLT #0 */ + tmp2 = tcg_const_i32(0); + gen_helper_neon_cgt_f32(tmp, cpu_env, tmp2, tmp); + tcg_temp_free(tmp2); + break; case 30: /* Float VABS */ gen_vfp_abs(0); break; -- 1.7.1