From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 10/24] target-alpha: Tidy up arithmetic exceptions.
Date: Tue, 19 Apr 2011 08:04:47 -0700 [thread overview]
Message-ID: <1303225501-12778-11-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1303225501-12778-1-git-send-email-rth@twiddle.net>
Introduce and use arith_excp, filling in the trap_arg[01] IPRs.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-alpha/op_helper.c | 34 +++++++++++++++++++++-------------
1 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index bbf89fe..9c19c96 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -32,6 +32,15 @@ void QEMU_NORETURN helper_excp (int excp, int error)
cpu_loop_exit();
}
+static void QEMU_NORETURN arith_excp(int exc, uint64_t mask)
+{
+ env->exception_index = EXCP_ARITH;
+ env->error_code = 0;
+ env->trap_arg0 = exc;
+ env->trap_arg1 = mask;
+ cpu_loop_exit();
+}
+
uint64_t helper_load_pcc (void)
{
/* ??? This isn't a timer for which we have any rate info. */
@@ -53,7 +62,7 @@ uint64_t helper_addqv (uint64_t op1, uint64_t op2)
uint64_t tmp = op1;
op1 += op2;
if (unlikely((tmp ^ op2 ^ (-1ULL)) & (tmp ^ op1) & (1ULL << 63))) {
- helper_excp(EXCP_ARITH, EXC_M_IOV);
+ arith_excp(EXC_M_IOV, 0);
}
return op1;
}
@@ -63,7 +72,7 @@ uint64_t helper_addlv (uint64_t op1, uint64_t op2)
uint64_t tmp = op1;
op1 = (uint32_t)(op1 + op2);
if (unlikely((tmp ^ op2 ^ (-1UL)) & (tmp ^ op1) & (1UL << 31))) {
- helper_excp(EXCP_ARITH, EXC_M_IOV);
+ arith_excp(EXC_M_IOV, 0);
}
return op1;
}
@@ -73,7 +82,7 @@ uint64_t helper_subqv (uint64_t op1, uint64_t op2)
uint64_t res;
res = op1 - op2;
if (unlikely((op1 ^ op2) & (res ^ op1) & (1ULL << 63))) {
- helper_excp(EXCP_ARITH, EXC_M_IOV);
+ arith_excp(EXC_M_IOV, 0);
}
return res;
}
@@ -83,7 +92,7 @@ uint64_t helper_sublv (uint64_t op1, uint64_t op2)
uint32_t res;
res = op1 - op2;
if (unlikely((op1 ^ op2) & (res ^ op1) & (1UL << 31))) {
- helper_excp(EXCP_ARITH, EXC_M_IOV);
+ arith_excp(EXC_M_IOV, 0);
}
return res;
}
@@ -93,7 +102,7 @@ uint64_t helper_mullv (uint64_t op1, uint64_t op2)
int64_t res = (int64_t)op1 * (int64_t)op2;
if (unlikely((int32_t)res != res)) {
- helper_excp(EXCP_ARITH, EXC_M_IOV);
+ arith_excp(EXC_M_IOV, 0);
}
return (int64_t)((int32_t)res);
}
@@ -105,7 +114,7 @@ uint64_t helper_mulqv (uint64_t op1, uint64_t op2)
muls64(&tl, &th, op1, op2);
/* If th != 0 && th != -1, then we had an overflow */
if (unlikely((th + 1) > 1)) {
- helper_excp(EXCP_ARITH, EXC_M_IOV);
+ arith_excp(EXC_M_IOV, 0);
}
return tl;
}
@@ -373,8 +382,6 @@ void helper_fp_exc_raise(uint32_t exc, uint32_t regno)
if (exc) {
uint32_t hw_exc = 0;
- env->trap_arg1 = 1ull << regno;
-
if (exc & float_flag_invalid) {
hw_exc |= EXC_M_INV;
}
@@ -390,7 +397,8 @@ void helper_fp_exc_raise(uint32_t exc, uint32_t regno)
if (exc & float_flag_inexact) {
hw_exc |= EXC_M_INE;
}
- helper_excp(EXCP_ARITH, hw_exc);
+
+ arith_excp(hw_exc, 1ull << regno);
}
}
@@ -420,7 +428,7 @@ uint64_t helper_ieee_input(uint64_t val)
if (env->fpcr_dnz) {
val &= 1ull << 63;
} else {
- helper_excp(EXCP_ARITH, EXC_M_UNF);
+ arith_excp(EXC_M_UNF, 0);
}
}
} else if (exp == 0x7ff) {
@@ -428,7 +436,7 @@ uint64_t helper_ieee_input(uint64_t val)
/* ??? I'm not sure these exception bit flags are correct. I do
know that the Linux kernel, at least, doesn't rely on them and
just emulates the insn to figure out what exception to use. */
- helper_excp(EXCP_ARITH, frac ? EXC_M_INV : EXC_M_FOV);
+ arith_excp(frac ? EXC_M_INV : EXC_M_FOV, 0);
}
return val;
}
@@ -445,12 +453,12 @@ uint64_t helper_ieee_input_cmp(uint64_t val)
if (env->fpcr_dnz) {
val &= 1ull << 63;
} else {
- helper_excp(EXCP_ARITH, EXC_M_UNF);
+ arith_excp(EXC_M_UNF, 0);
}
}
} else if (exp == 0x7ff && frac) {
/* NaN. */
- helper_excp(EXCP_ARITH, EXC_M_INV);
+ arith_excp(EXC_M_INV, 0);
}
return val;
}
--
1.7.3.4
next prev parent reply other threads:[~2011-04-19 15:41 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-19 15:04 [Qemu-devel] [PATCH 00/24] Alpha system emulation, v2 Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 01/24] Export the unassigned_mem read/write functions Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 02/24] target-alpha: Disassemble EV6 PALcode instructions Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 03/24] pci: Export pci_to_cpu_addr Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 04/24] target-alpha: Remove partial support for palcode emulation Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 05/24] target-alpha: Tidy exception constants Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 06/24] target-alpha: Rationalize internal processor registers Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 07/24] target-alpha: Cleanup MMU modes Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 08/24] target-alpha: Fixup translation of PALmode instructions Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 09/24] target-alpha: Add IPRs to be used by the emulation PALcode Richard Henderson
2011-04-19 15:04 ` Richard Henderson [this message]
2011-04-19 15:04 ` [Qemu-devel] [PATCH 11/24] target-alpha: Merge HW_REI and HW_RET implementations Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 12/24] target-alpha: Implement do_interrupt for system mode Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 13/24] target-alpha: Swap shadow registers moving to/from PALmode Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 14/24] target-alpha: Add various symbolic constants Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 15/24] target-alpha: All ISA checks to use TB->FLAGS Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 16/24] target-alpha: Disable interrupts properly Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 17/24] target-alpha: Implement more CALL_PAL values inline Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 18/24] target-alpha: Add custom PALcode image for SX164 emulation Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 19/24] target-alpha: Implement cpu_alpha_handle_mmu_fault for system mode Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 20/24] target-alpha: Trap for unassigned and unaligned addresses Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 21/24] target-alpha: Include the PCC_OFS in the RPCC return value Richard Henderson
2011-04-19 15:04 ` [Qemu-devel] [PATCH 22/24] target-alpha: Implement TLB flush primitives Richard Henderson
2011-04-19 15:05 ` [Qemu-devel] [PATCH 23/24] target-alpha: Enable the alpha-softmmu target Richard Henderson
2011-04-19 15:05 ` [Qemu-devel] [PATCH 24/24] target-alpha: Add SX164 emulation Richard Henderson
2011-04-20 9:06 ` [Qemu-devel] [PATCH 00/24] Alpha system emulation, v2 Tristan Gingold
2011-04-20 14:13 ` Brian Wheeler
2011-04-20 14:46 ` Richard Henderson
2011-04-20 15:46 ` Tristan Gingold
2011-04-20 15:54 ` Richard Henderson
2011-04-21 12:31 ` Tristan Gingold
2011-04-21 13:37 ` Brian Wheeler
2011-04-21 13:43 ` Tristan Gingold
2011-04-21 14:48 ` Brian Wheeler
2011-04-21 14:57 ` Richard Henderson
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