From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:47667) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBM-0004qv-NZ for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFYBM-0005Ya-1p for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:28 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:41034) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBL-0005Xk-TN for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:28 -0400 Received: by mail-pz0-f45.google.com with SMTP id 30so2296231pzk.4 for ; Thu, 28 Apr 2011 13:51:27 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 28 Apr 2011 13:50:45 -0700 Message-Id: <1304023875-25040-4-git-send-email-rth@twiddle.net> In-Reply-To: <1304023875-25040-1-git-send-email-rth@twiddle.net> References: <1304023875-25040-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 03/33] target-alpha: Disassemble EV6 PALcode instructions. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The QEMU emulation PALcode will use EV6 PALcode insns regardless of the "real" cpu instruction set being emulated. Signed-off-by: Richard Henderson --- alpha-dis.c | 4 ---- dis-asm.h | 3 +++ disas.c | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/alpha-dis.c b/alpha-dis.c index 8a2411e..ae331b3 100644 --- a/alpha-dis.c +++ b/alpha-dis.c @@ -238,10 +238,6 @@ extern const unsigned alpha_num_operands; #define AXP_REG_SP 30 #define AXP_REG_ZERO 31 -#define bfd_mach_alpha_ev4 0x10 -#define bfd_mach_alpha_ev5 0x20 -#define bfd_mach_alpha_ev6 0x30 - enum bfd_reloc_code_real { BFD_RELOC_23_PCREL_S2, BFD_RELOC_ALPHA_HINT diff --git a/dis-asm.h b/dis-asm.h index 296537a..5b07d7f 100644 --- a/dis-asm.h +++ b/dis-asm.h @@ -184,6 +184,9 @@ enum bfd_architecture #define bfd_mach_sh5 0x50 bfd_arch_alpha, /* Dec Alpha */ #define bfd_mach_alpha 1 +#define bfd_mach_alpha_ev4 0x10 +#define bfd_mach_alpha_ev5 0x20 +#define bfd_mach_alpha_ev6 0x30 bfd_arch_arm, /* Advanced Risc Machines ARM */ #define bfd_mach_arm_unknown 0 #define bfd_mach_arm_2 1 diff --git a/disas.c b/disas.c index 223606c..d208c52 100644 --- a/disas.c +++ b/disas.c @@ -205,7 +205,7 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) disasm_info.mach = bfd_mach_sh4; print_insn = print_insn_sh; #elif defined(TARGET_ALPHA) - disasm_info.mach = bfd_mach_alpha; + disasm_info.mach = bfd_mach_alpha_ev6; print_insn = print_insn_alpha; #elif defined(TARGET_CRIS) if (flags != 32) { -- 1.7.4.4