From: Stefan Weil <weil@mail.berlios.de>
To: QEMU Developers <qemu-devel@nongnu.org>
Cc: qemu-trivial@nongnu.org
Subject: [Qemu-devel] [PATCH] Fix typos in comments (chek -> check)
Date: Sat, 30 Apr 2011 22:49:26 +0200 [thread overview]
Message-ID: <1304196566-14909-1-git-send-email-weil@mail.berlios.de> (raw)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
---
exec.c | 2 +-
target-ppc/STATUS | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index c3dc68a..ed7cffa 100644
--- a/exec.c
+++ b/exec.c
@@ -2041,7 +2041,7 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
/* we modify the TLB cache so that the dirty bit will be set again
when accessing the range */
start1 = (unsigned long)qemu_safe_ram_ptr(start);
- /* Chek that we don't span multiple blocks - this breaks the
+ /* Check that we don't span multiple blocks - this breaks the
address comparisons below. */
if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1
!= (end - 1) - start) {
diff --git a/target-ppc/STATUS b/target-ppc/STATUS
index 32e7ffa..c8e9018 100644
--- a/target-ppc/STATUS
+++ b/target-ppc/STATUS
@@ -11,7 +11,7 @@ INSN: instruction set.
SPR: special purpose registers set
OK => all SPR registered (but some may be fake)
KO => some SPR are missing or should be removed
- ? => uncheked
+ ? => unchecked
MSR: MSR bits definitions
OK => all MSR bits properly defined
KO => MSR definition is incorrect
--
1.7.2.5
next reply other threads:[~2011-04-30 20:49 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-30 20:49 Stefan Weil [this message]
2011-05-08 12:01 ` [Qemu-devel] [PATCH] Fix typos in comments (chek -> check) Stefan Hajnoczi
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