From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:49124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QGIag-0007lS-PW for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QGIaf-0004hX-W6 for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:42 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:42205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QGIaf-0004hP-PB for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:41 -0400 Received: by pzk30 with SMTP id 30so3274281pzk.4 for ; Sat, 30 Apr 2011 15:24:40 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Sat, 30 Apr 2011 15:24:25 -0700 Message-Id: <1304202271-24730-3-git-send-email-rth@twiddle.net> In-Reply-To: <1304202271-24730-1-git-send-email-rth@twiddle.net> References: <1304202271-24730-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 2/8] irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Aurelien Jarno This mask contains all of the bits that should be ignored while single stepping in the debugger. The mask contains 2 bits that are not currently cleared, but are also never set. The bits are included in the mask for consistency in handling of the CPU_INTERRUPT_TGT_EXT_N bits. Signed-off-by: Richard Henderson --- cpu-all.h | 8 ++++++++ cpu-exec.c | 5 +---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index 8c3222e..f813ef8 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -837,6 +837,14 @@ extern CPUState *cpu_single_env; #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 +/* The set of all bits that should be masked when single-stepping. */ +#define CPU_INTERRUPT_SSTEP_MASK \ + (CPU_INTERRUPT_HARD \ + | CPU_INTERRUPT_TGT_EXT_0 \ + | CPU_INTERRUPT_TGT_EXT_1 \ + | CPU_INTERRUPT_TGT_EXT_2 \ + | CPU_INTERRUPT_TGT_EXT_3 \ + | CPU_INTERRUPT_TGT_EXT_4) void cpu_interrupt(CPUState *s, int mask); void cpu_reset_interrupt(CPUState *env, int mask); diff --git a/cpu-exec.c b/cpu-exec.c index 395cd8c..5b42b25 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -360,10 +360,7 @@ int cpu_exec(CPUState *env1) if (unlikely(interrupt_request)) { if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) { /* Mask out external interrupts for this step. */ - interrupt_request &= ~(CPU_INTERRUPT_HARD | - CPU_INTERRUPT_FIQ | - CPU_INTERRUPT_SMI | - CPU_INTERRUPT_NMI); + interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK; } if (interrupt_request & CPU_INTERRUPT_DEBUG) { env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; -- 1.7.4.4