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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 7/8] target-i386: Privatize some i386-specific interrupt names.
Date: Sat, 30 Apr 2011 15:24:30 -0700	[thread overview]
Message-ID: <1304202271-24730-8-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1304202271-24730-1-git-send-email-rth@twiddle.net>

SMI, VIRQ, INIT, SIPI, and MCE are all only used by the i386 port.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cpu-all.h         |    5 -----
 poison.h          |    2 --
 target-i386/cpu.h |    8 ++++++++
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/cpu-all.h b/cpu-all.h
index 88c8361..1ecf42b 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -828,12 +828,7 @@ extern CPUState *cpu_single_env;
 
 /* Temporary remapping from the generic names back to the previous
    cpu-specific names.  These will be moved to target-foo/cpu.h next.  */
-#define CPU_INTERRUPT_SMI	CPU_INTERRUPT_TGT_EXT_2
-#define CPU_INTERRUPT_VIRQ	CPU_INTERRUPT_TGT_INT_0
 #define CPU_INTERRUPT_NMI	CPU_INTERRUPT_TGT_EXT_3
-#define CPU_INTERRUPT_INIT	CPU_INTERRUPT_TGT_INT_1
-#define CPU_INTERRUPT_SIPI	CPU_INTERRUPT_TGT_INT_2
-#define CPU_INTERRUPT_MCE	CPU_INTERRUPT_TGT_EXT_4
 
 /* The set of all bits that should be masked when single-stepping.  */
 #define CPU_INTERRUPT_SSTEP_MASK \
diff --git a/poison.h b/poison.h
index 787f8e9..4fcf46d 100644
--- a/poison.h
+++ b/poison.h
@@ -40,9 +40,7 @@
 #pragma GCC poison CPU_INTERRUPT_HARD
 #pragma GCC poison CPU_INTERRUPT_EXITTB
 #pragma GCC poison CPU_INTERRUPT_HALT
-#pragma GCC poison CPU_INTERRUPT_SMI
 #pragma GCC poison CPU_INTERRUPT_DEBUG
-#pragma GCC poison CPU_INTERRUPT_VIRQ
 #pragma GCC poison CPU_INTERRUPT_NMI
 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index c7047d5..01880f9 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -466,6 +466,14 @@
 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
                                  for syscall instruction */
 
+/* i386-specific interrupt pending bits.  */
+#define CPU_INTERRUPT_SMI	CPU_INTERRUPT_TGT_EXT_2
+#define CPU_INTERRUPT_MCE	CPU_INTERRUPT_TGT_EXT_4
+#define CPU_INTERRUPT_VIRQ	CPU_INTERRUPT_TGT_INT_0
+#define CPU_INTERRUPT_INIT	CPU_INTERRUPT_TGT_INT_1
+#define CPU_INTERRUPT_SIPI	CPU_INTERRUPT_TGT_INT_2
+
+
 enum {
     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
-- 
1.7.4.4

  parent reply	other threads:[~2011-04-30 22:24 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-04-30 22:24 [Qemu-devel] [PATCH 0/8] cpu interrupt cleanup Richard Henderson
2011-04-30 22:24 ` [Qemu-devel] [PATCH 1/8] irq: Introduce CPU_INTERRUPT_TGT_* defines Richard Henderson
2011-04-30 22:24 ` [Qemu-devel] [PATCH 2/8] irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK Richard Henderson
2011-04-30 22:24 ` [Qemu-devel] [PATCH 3/8] target-mips: Do not check CPU_INTERRUPT_TIMER Richard Henderson
2011-04-30 22:24 ` [Qemu-devel] [PATCH 4/8] target-sparc: " Richard Henderson
2011-04-30 22:24 ` [Qemu-devel] [PATCH 5/8] irq: Remove CPU_INTERRUPT_TIMER Richard Henderson
2011-04-30 22:24 ` [Qemu-devel] [PATCH 6/8] target-arm: Privatize CPU_INTERRUPT_FIQ Richard Henderson
2011-04-30 22:24 ` Richard Henderson [this message]
2011-04-30 22:24 ` [Qemu-devel] [PATCH 8/8] irq: Privatize CPU_INTERRUPT_NMI Richard Henderson
2011-04-30 22:36 ` [Qemu-devel] [PATCH 0/8] cpu interrupt cleanup Richard Henderson
2011-05-01  8:18   ` Jan Kiszka
2011-05-01 14:59     ` Richard Henderson
2011-05-01 17:31       ` Jan Kiszka
2011-05-04 19:19 ` Blue Swirl
  -- strict thread matches above, loose matches on Subject: below --
2011-05-04 20:34 [Qemu-devel] [PATCH 0/8] cpu interrupt cleanup, v2 Richard Henderson
2011-05-04 20:34 ` [Qemu-devel] [PATCH 7/8] target-i386: Privatize some i386-specific interrupt names Richard Henderson

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