From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:49272) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QGIam-0007vT-32 for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QGIak-0004kS-Vj for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:47 -0400 Received: from mail-pw0-f45.google.com ([209.85.160.45]:55698) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QGIak-0004gz-Oc for qemu-devel@nongnu.org; Sat, 30 Apr 2011 18:24:46 -0400 Received: by mail-pw0-f45.google.com with SMTP id 6so2851739pwi.4 for ; Sat, 30 Apr 2011 15:24:46 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Sat, 30 Apr 2011 15:24:30 -0700 Message-Id: <1304202271-24730-8-git-send-email-rth@twiddle.net> In-Reply-To: <1304202271-24730-1-git-send-email-rth@twiddle.net> References: <1304202271-24730-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 7/8] target-i386: Privatize some i386-specific interrupt names. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Aurelien Jarno SMI, VIRQ, INIT, SIPI, and MCE are all only used by the i386 port. Signed-off-by: Richard Henderson --- cpu-all.h | 5 ----- poison.h | 2 -- target-i386/cpu.h | 8 ++++++++ 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index 88c8361..1ecf42b 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -828,12 +828,7 @@ extern CPUState *cpu_single_env; /* Temporary remapping from the generic names back to the previous cpu-specific names. These will be moved to target-foo/cpu.h next. */ -#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 -#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 -#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 -#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 -#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 /* The set of all bits that should be masked when single-stepping. */ #define CPU_INTERRUPT_SSTEP_MASK \ diff --git a/poison.h b/poison.h index 787f8e9..4fcf46d 100644 --- a/poison.h +++ b/poison.h @@ -40,9 +40,7 @@ #pragma GCC poison CPU_INTERRUPT_HARD #pragma GCC poison CPU_INTERRUPT_EXITTB #pragma GCC poison CPU_INTERRUPT_HALT -#pragma GCC poison CPU_INTERRUPT_SMI #pragma GCC poison CPU_INTERRUPT_DEBUG -#pragma GCC poison CPU_INTERRUPT_VIRQ #pragma GCC poison CPU_INTERRUPT_NMI #pragma GCC poison CPU_INTERRUPT_TGT_EXT_0 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_1 diff --git a/target-i386/cpu.h b/target-i386/cpu.h index c7047d5..01880f9 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -466,6 +466,14 @@ #define EXCP_SYSCALL 0x100 /* only happens in user only emulation for syscall instruction */ +/* i386-specific interrupt pending bits. */ +#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 +#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 +#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 +#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 +#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 + + enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ -- 1.7.4.4