From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:53030) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQRz-0004YT-Ps for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHQRy-0000kj-U9 for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:23 -0400 Received: from mail-ew0-f45.google.com ([209.85.215.45]:56465) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQRy-0000ZL-NQ for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:22 -0400 Received: by mail-ew0-f45.google.com with SMTP id 24so221435ewy.4 for ; Tue, 03 May 2011 18:00:22 -0700 (PDT) From: Max Filippov Date: Wed, 4 May 2011 04:59:10 +0400 Message-Id: <1304470768-16924-10-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> References: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [RFC 10/28] target-xtensa: add special and user registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Max Filippov Special Registers hold the majority of the state added to the processor by the options. See ISA, 5.3 for details. User Registers hold state added in support of designer’s TIE and in some cases of options that Tensilica provides. See ISA, 5.4 for details. Only registers mapped in sregnames or uregnames are considered valid. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 7 ++++++ target-xtensa/translate.c | 47 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index cf19fce..e99e3bb 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -99,6 +99,12 @@ enum { XTENSA_OPTIN_TRACE_PORT, }; +enum { + THREADPTR = 231, + FCR = 232, + FSR = 233, +}; + typedef struct XtensaConfig { const char *name; uint64_t options; @@ -109,6 +115,7 @@ typedef struct CPUXtensaState { uint32_t regs[16]; uint32_t pc; uint32_t sregs[256]; + uint32_t uregs[256]; CPU_COMMON } CPUXtensaState; diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index f4d74e0..f1f01bc 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -51,9 +51,20 @@ typedef struct DisasContext { static TCGv_ptr cpu_env; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; +static TCGv_i32 cpu_SR[256]; +static TCGv_i32 cpu_UR[256]; #include "gen-icount.h" +static const char * const sregnames[256] = { +}; + +static const char * const uregnames[256] = { + [THREADPTR] = "THREADPTR", + [FCR] = "FCR", + [FSR] = "FSR", +}; + void xtensa_translate_init(void) { static const char * const regnames[] = { @@ -73,6 +84,22 @@ void xtensa_translate_init(void) offsetof(CPUState, regs[i]), regnames[i]); } + + for (i = 0; i < 256; ++i) { + if (sregnames[i]) { + cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, sregs[i]), + sregnames[i]); + } + } + + for (i = 0; i < 256; ++i) { + if (uregnames[i]) { + cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, uregs[i]), + uregnames[i]); + } + } } static void gen_exception(int excp) @@ -737,9 +764,25 @@ void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, int flags) { - int i; + int i, j; + + cpu_fprintf(f, "PC=%08x\n\n", env->pc); + + for (i = j = 0; i < 256; ++i) + if (sregnames[i]) { + cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i], + (j++ % 4) == 3 ? '\n' : ' '); + } + + cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); + + for (i = j = 0; i < 256; ++i) + if (uregnames[i]) { + cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i], + (j++ % 4) == 3 ? '\n' : ' '); + } - cpu_fprintf(f, "PC=%08x\n", env->pc); + cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); for (i = 0; i < 16; ++i) cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i], -- 1.7.3.4