From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:53152) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQSH-00051N-WA for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHQSH-0000ne-45 for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:41 -0400 Received: from mail-ey0-f173.google.com ([209.85.215.173]:37946) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQSG-0000XK-TI for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:41 -0400 Received: by mail-ey0-f173.google.com with SMTP id 6so222869eyb.4 for ; Tue, 03 May 2011 18:00:40 -0700 (PDT) From: Max Filippov Date: Wed, 4 May 2011 04:59:17 +0400 Message-Id: <1304470768-16924-17-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> References: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [RFC 17/28] target-xtensa: implement CACHE group List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Max Filippov All operations in this group are no-ops, because cache ought to be transparent to applications. However cache may be abused, then we'll need to actually implement these opcodes. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 95 ++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 94 insertions(+), 1 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 3959d80..4b5edc3 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -919,7 +919,100 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 7: /*CACHEc*/ - TBD(); + if (RRI8_T < 8) { + HAS_OPTION(XTENSA_OPTION_DCACHE); + } + + switch (RRI8_T) { + case 0: /*DPFRc*/ + break; + + case 1: /*DPFWc*/ + break; + + case 2: /*DPFROc*/ + break; + + case 3: /*DPFWOc*/ + break; + + case 4: /*DHWBc*/ + break; + + case 5: /*DHWBIc*/ + break; + + case 6: /*DHIc*/ + break; + + case 7: /*DIIc*/ + break; + + case 8: /*DCEc*/ + switch (_OP1) { + case 0: /*DPFLl*/ + HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); + break; + + case 2: /*DHUl*/ + HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); + break; + + case 3: /*DIUl*/ + HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); + break; + + case 4: /*DIWBc*/ + HAS_OPTION(XTENSA_OPTION_DCACHE); + break; + + case 5: /*DIWBIc*/ + HAS_OPTION(XTENSA_OPTION_DCACHE); + break; + + default: /*reserved*/ + RESERVED(); + break; + + } + break; + + case 12: /*IPFc*/ + HAS_OPTION(XTENSA_OPTION_ICACHE); + break; + + case 13: /*ICEc*/ + switch (_OP1) { + case 0: /*IPFLl*/ + HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); + break; + + case 2: /*IHUl*/ + HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); + break; + + case 3: /*IIUl*/ + HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); + break; + + default: /*reserved*/ + RESERVED(); + break; + } + break; + + case 14: /*IHIc*/ + HAS_OPTION(XTENSA_OPTION_ICACHE); + break; + + case 15: /*IIIc*/ + HAS_OPTION(XTENSA_OPTION_ICACHE); + break; + + default: /*reserved*/ + RESERVED(); + break; + } break; case 9: /*L16SI*/ -- 1.7.3.4