From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:53232) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQSV-0005Ra-8P for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHQSU-0000pQ-Db for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:55 -0400 Received: from mail-ew0-f45.google.com ([209.85.215.45]:56465) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQSU-0000ZL-91 for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:54 -0400 Received: by mail-ew0-f45.google.com with SMTP id 24so221435ewy.4 for ; Tue, 03 May 2011 18:00:53 -0700 (PDT) From: Max Filippov Date: Wed, 4 May 2011 04:59:22 +0400 Message-Id: <1304470768-16924-22-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> References: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [RFC 22/28] target-xtensa: implement extended L32R List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Max Filippov See ISA, 4.3.3 for details. Enable bit of LITBASE may be stored separately for further speedup. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 1 + target-xtensa/helper.c | 1 + target-xtensa/translate.c | 18 ++++++++++++++++-- 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 7fade0c..8110665 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -110,6 +110,7 @@ enum { LEND = 1, LCOUNT = 2, SAR = 3, + LITBASE = 5, SCOMPARE1 = 12, WINDOW_BASE = 72, WINDOW_START = 73, diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 61d1ab3..6df2e50 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -38,6 +38,7 @@ void cpu_reset(CPUXtensaState *env) { env->exception_taken = 0; env->pc = env->config->exception_vector[EXC_RESET]; + env->sregs[LITBASE] &= ~1; env->sregs[PS] = 0x1f; } diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index e33c2fa..53e0d02 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -62,6 +62,7 @@ static const char * const sregnames[256] = { [LEND] = "LEND", [LCOUNT] = "LCOUNT", [SAR] = "SAR", + [LITBASE] = "LITBASE", [SCOMPARE1] = "SCOMPARE1", [WINDOW_BASE] = "WINDOW_BASE", [WINDOW_START] = "WINDOW_START", @@ -1168,12 +1169,25 @@ static void disas_xtensa_insn(DisasContext *dc) case 1: /*L32R*/ { - TCGv_i32 tmp = tcg_const_i32( + TCGv_i32 tmp = tcg_temp_local_new_i32(); + + tcg_gen_movi_i32(tmp, (0xfffc0000 | (RI16_IMM16 << 2)) + ((dc->pc + 3) & ~3)); - /* no ext L32R */ + if (option_enabled(dc, XTENSA_OPTION_EXTENDED_L32R)) { + TCGv_i32 tmp1 = tcg_temp_new_i32(); + int label = gen_new_label(); + + tcg_gen_andi_i32(tmp1, cpu_SR[LITBASE], 1); + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp1, 0, label); + tcg_gen_andi_i32(tmp1, cpu_SR[LITBASE], 0xfffff000); + tcg_gen_addi_i32(tmp, tmp1, (0xfffc0000 | (RI16_IMM16 << 2))); + gen_set_label(label); + tcg_temp_free(tmp1); + } + /* much simplified, no MMU */ tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, 0); tcg_temp_free(tmp); } -- 1.7.3.4