From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:52905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQRi-00042q-Uw for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHQRh-0000fy-QD for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:06 -0400 Received: from mail-ey0-f173.google.com ([209.85.215.173]:37946) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQRh-0000XK-LH for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:05 -0400 Received: by mail-ey0-f173.google.com with SMTP id 6so222869eyb.4 for ; Tue, 03 May 2011 18:00:05 -0700 (PDT) From: Max Filippov Date: Wed, 4 May 2011 04:59:04 +0400 Message-Id: <1304470768-16924-4-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> References: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [RFC 04/28] target-xtensa: implement narrow instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Max Filippov Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 57 insertions(+), 0 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 16efcfd..26fc28b 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -301,22 +301,79 @@ static void disas_xtensa_insn(DisasContext *dc) case 7: /*B*/ break; +#define gen_narrow_load_store(type) do { \ + TCGv_i32 addr = tcg_temp_new_i32(); \ + tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \ + tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \ + tcg_temp_free(addr); \ + } while (0) + case 8: /*L32I.Nn*/ + gen_narrow_load_store(ld32u); break; case 9: /*S32I.Nn*/ + gen_narrow_load_store(st32); break; +#undef gen_narrow_load_store case 10: /*ADD.Nn*/ + tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]); break; case 11: /*ADDI.Nn*/ + tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1); break; case 12: /*ST2n*/ + if (RRRN_T < 8) { /*MOVI.Nn*/ + tcg_gen_movi_i32(cpu_R[RRRN_S], + RRRN_R | (RRRN_T << 4) | + ((RRRN_T & 6) == 6 ? 0xffffff80 : 0)); + } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/ + int label = gen_new_label(); + int inv = RRRN_T & 4; + + tcg_gen_brcondi_i32(inv ? TCG_COND_EQ : TCG_COND_NE, + cpu_R[RRRN_S], 0, label); + gen_jumpi(dc, dc->pc + 4 + (RRRN_R | ((RRRN_T & 3) << 4))); + gen_set_label(label); + gen_jumpi(dc, dc->pc + 2); + } break; case 13: /*ST3n*/ + switch (RRRN_R) { + case 0: /*MOV.Nn*/ + tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]); + break; + + case 15: /*S3*/ + switch (RRRN_T) { + case 0: /*RET.Nn*/ + gen_jump(dc, cpu_R[0]); + break; + + case 1: /*RETW.Nn*/ + break; + + case 2: /*BREAK.Nn*/ + break; + + case 3: /*NOP.Nn*/ + break; + + case 6: /*ILL.Nn*/ + break; + + default: /*reserved*/ + break; + } + break; + + default: /*reserved*/ + break; + } break; default: /*reserved*/ -- 1.7.3.4