[Qemu-devel] [PATCH 0/8] cpu interrupt cleanup, v2

[Qemu-devel] [PATCH 0/8] cpu interrupt cleanup, v2

[Richard Henderson]

v1->v2
  Rebase vs HEAD (d2d979c)
  Cleanup whitespace errors.


r~

Richard Henderson (8):
  irq: Introduce CPU_INTERRUPT_TGT_* defines.
  irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK.
  target-mips: Do not check CPU_INTERRUPT_TIMER.
  target-sparc: Do not check CPU_INTERRUPT_TIMER.
  irq: Remove CPU_INTERRUPT_TIMER.
  target-arm: Privatize CPU_INTERRUPT_FIQ.
  target-i386: Privatize some i386-specific interrupt names.
  irq: Privatize CPU_INTERRUPT_NMI.

 cpu-all.h               |   60 +++++++++++++++++++++++++++++++++++++---------
 cpu-exec.c              |    8 +-----
 poison.h                |   13 ++++++----
 target-arm/cpu.h        |    4 +++
 target-cris/cpu.h       |    3 ++
 target-i386/cpu.h       |    9 +++++++
 target-microblaze/cpu.h |    3 ++
 target-mips/exec.h      |    4 ---
 8 files changed, 76 insertions(+), 28 deletions(-)

-- 
1.7.4.4

[Qemu-devel] [PATCH 1/8] irq: Introduce CPU_INTERRUPT_TGT_* defines.

[Richard Henderson]

These defines will be place-holders for cpu-specific functionality.
Generic code will, at the end of the patch series, no longer have to
concern itself about how SMI, NMI, etc should be handled.  Instead,
generic code will know only that the interrupt is internal or external.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cpu-all.h |   63 +++++++++++++++++++++++++++++++++++++++++++++++++-----------
 poison.h  |    8 +++++++
 2 files changed, 59 insertions(+), 12 deletions(-)

diff --git a/cpu-all.h b/cpu-all.h
index 88126ea..dd9c230 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -786,18 +786,57 @@ void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...)
 extern CPUState *first_cpu;
 extern CPUState *cpu_single_env;
 
-#define CPU_INTERRUPT_HARD   0x02 /* hardware interrupt pending */
-#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
-#define CPU_INTERRUPT_TIMER  0x08 /* internal timer exception pending */
-#define CPU_INTERRUPT_FIQ    0x10 /* Fast interrupt pending.  */
-#define CPU_INTERRUPT_HALT   0x20 /* CPU halt wanted */
-#define CPU_INTERRUPT_SMI    0x40 /* (x86 only) SMI interrupt pending */
-#define CPU_INTERRUPT_DEBUG  0x80 /* Debug event occured.  */
-#define CPU_INTERRUPT_VIRQ   0x100 /* virtual interrupt pending.  */
-#define CPU_INTERRUPT_NMI    0x200 /* NMI pending. */
-#define CPU_INTERRUPT_INIT   0x400 /* INIT pending. */
-#define CPU_INTERRUPT_SIPI   0x800 /* SIPI pending. */
-#define CPU_INTERRUPT_MCE    0x1000 /* (x86 only) MCE pending. */
+/* Flags for use in ENV->INTERRUPT_PENDING.
+
+   The numbers assigned here are non-sequential in order to preserve
+   binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
+   previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
+   the vmstate dump.  */
+
+/* External hardware interrupt pending.  This is typically used for
+   interrupts from devices.  */
+#define CPU_INTERRUPT_HARD        0x0002
+
+/* Exit the current TB.  This is typically used when some system-level device
+   makes some change to the memory mapping.  E.g. the a20 line change.  */
+#define CPU_INTERRUPT_EXITTB      0x0004
+
+/* Halt the CPU.  */
+#define CPU_INTERRUPT_HALT        0x0020
+
+/* Debug event pending.  */
+#define CPU_INTERRUPT_DEBUG       0x0080
+
+/* Several target-specific external hardware interrupts.  Each target/cpu.h
+   should define proper names based on these defines.  */
+#define CPU_INTERRUPT_TGT_EXT_0   0x0008
+#define CPU_INTERRUPT_TGT_EXT_1   0x0010
+#define CPU_INTERRUPT_TGT_EXT_2   0x0040
+#define CPU_INTERRUPT_TGT_EXT_3   0x0200
+#define CPU_INTERRUPT_TGT_EXT_4   0x1000
+
+/* Several target-specific internal interrupts.  These differ from the
+   preceeding target-specific interrupts in that they are intended to
+   originate from within the cpu itself, typically in response to some
+   instruction being executed.  These, therefore, are not masked while
+   single-stepping within the debugger.  */
+#define CPU_INTERRUPT_TGT_INT_0   0x0100
+#define CPU_INTERRUPT_TGT_INT_1   0x0400
+#define CPU_INTERRUPT_TGT_INT_2   0x0800
+
+/* First unused bit: 0x2000.  */
+
+/* Temporary remapping from the generic names back to the previous
+   cpu-specific names.  These will be moved to target-foo/cpu.h next.  */
+#define CPU_INTERRUPT_TIMER       CPU_INTERRUPT_TGT_EXT_0
+#define CPU_INTERRUPT_FIQ         CPU_INTERRUPT_TGT_EXT_1
+#define CPU_INTERRUPT_SMI         CPU_INTERRUPT_TGT_EXT_2
+#define CPU_INTERRUPT_VIRQ        CPU_INTERRUPT_TGT_INT_0
+#define CPU_INTERRUPT_NMI         CPU_INTERRUPT_TGT_EXT_3
+#define CPU_INTERRUPT_INIT        CPU_INTERRUPT_TGT_INT_1
+#define CPU_INTERRUPT_SIPI        CPU_INTERRUPT_TGT_INT_2
+#define CPU_INTERRUPT_MCE         CPU_INTERRUPT_TGT_EXT_4
+
 
 #ifndef CONFIG_USER_ONLY
 typedef void (*CPUInterruptHandler)(CPUState *, int);
diff --git a/poison.h b/poison.h
index 93c75fa..8fa3ee6 100644
--- a/poison.h
+++ b/poison.h
@@ -46,6 +46,14 @@
 #pragma GCC poison CPU_INTERRUPT_DEBUG
 #pragma GCC poison CPU_INTERRUPT_VIRQ
 #pragma GCC poison CPU_INTERRUPT_NMI
+#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
+#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
+#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2
+#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3
+#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4
+#pragma GCC poison CPU_INTERRUPT_TGT_INT_0
+#pragma GCC poison CPU_INTERRUPT_TGT_INT_1
+#pragma GCC poison CPU_INTERRUPT_TGT_INT_2
 
 #endif
 #endif
-- 
1.7.4.4

[Qemu-devel] [PATCH 2/8] irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK.

[Richard Henderson]

This mask contains all of the bits that should be ignored while single
stepping in the debugger.  The mask contains 2 bits that are not currently
cleared, but are also never set.  The bits are included in the mask for
consistency in handling of the CPU_INTERRUPT_TGT_EXT_N bits.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cpu-all.h  |    8 ++++++++
 cpu-exec.c |    5 +----
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/cpu-all.h b/cpu-all.h
index dd9c230..bc0dad8 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -837,6 +837,14 @@ extern CPUState *cpu_single_env;
 #define CPU_INTERRUPT_SIPI        CPU_INTERRUPT_TGT_INT_2
 #define CPU_INTERRUPT_MCE         CPU_INTERRUPT_TGT_EXT_4
 
+/* The set of all bits that should be masked when single-stepping.  */
+#define CPU_INTERRUPT_SSTEP_MASK \
+    (CPU_INTERRUPT_HARD          \
+     | CPU_INTERRUPT_TGT_EXT_0   \
+     | CPU_INTERRUPT_TGT_EXT_1   \
+     | CPU_INTERRUPT_TGT_EXT_2   \
+     | CPU_INTERRUPT_TGT_EXT_3   \
+     | CPU_INTERRUPT_TGT_EXT_4)
 
 #ifndef CONFIG_USER_ONLY
 typedef void (*CPUInterruptHandler)(CPUState *, int);
diff --git a/cpu-exec.c b/cpu-exec.c
index 395cd8c..5b42b25 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -360,10 +360,7 @@ int cpu_exec(CPUState *env1)
                 if (unlikely(interrupt_request)) {
                     if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
                         /* Mask out external interrupts for this step. */
-                        interrupt_request &= ~(CPU_INTERRUPT_HARD |
-                                               CPU_INTERRUPT_FIQ |
-                                               CPU_INTERRUPT_SMI |
-                                               CPU_INTERRUPT_NMI);
+                        interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
                     }
                     if (interrupt_request & CPU_INTERRUPT_DEBUG) {
                         env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
-- 
1.7.4.4

[Qemu-devel] [PATCH 3/8] target-mips: Do not check CPU_INTERRUPT_TIMER.

[Richard Henderson]

This bit is never set, therefore we should not read it either.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-mips/exec.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/target-mips/exec.h b/target-mips/exec.h
index b3c5a13..607edf1 100644
--- a/target-mips/exec.h
+++ b/target-mips/exec.h
@@ -29,10 +29,6 @@ static inline int cpu_has_work(CPUState *env)
         has_work = 1;
     }
 
-    if (env->interrupt_request & CPU_INTERRUPT_TIMER) {
-        has_work = 1;
-    }
-
     return has_work;
 }
 
-- 
1.7.4.4

[Qemu-devel] [PATCH 4/8] target-sparc: Do not check CPU_INTERRUPT_TIMER.

[Richard Henderson]

This bit is never set, therefore we should not read it either.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cpu-exec.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/cpu-exec.c b/cpu-exec.c
index 5b42b25..6d43726 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -489,9 +489,6 @@ int cpu_exec(CPUState *env1)
                                 next_tb = 0;
                             }
                         }
-		    } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
-			//do_interrupt(0, 0, 0, 0, 0);
-			env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 		    }
 #elif defined(TARGET_ARM)
                     if (interrupt_request & CPU_INTERRUPT_FIQ
-- 
1.7.4.4

[Qemu-devel] [PATCH 5/8] irq: Remove CPU_INTERRUPT_TIMER.

[Richard Henderson]

It is no longer used anywhere.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cpu-all.h |    1 -
 poison.h  |    1 -
 2 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/cpu-all.h b/cpu-all.h
index bc0dad8..a30943f 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -828,7 +828,6 @@ extern CPUState *cpu_single_env;
 
 /* Temporary remapping from the generic names back to the previous
    cpu-specific names.  These will be moved to target-foo/cpu.h next.  */
-#define CPU_INTERRUPT_TIMER       CPU_INTERRUPT_TGT_EXT_0
 #define CPU_INTERRUPT_FIQ         CPU_INTERRUPT_TGT_EXT_1
 #define CPU_INTERRUPT_SMI         CPU_INTERRUPT_TGT_EXT_2
 #define CPU_INTERRUPT_VIRQ        CPU_INTERRUPT_TGT_INT_0
diff --git a/poison.h b/poison.h
index 8fa3ee6..369d82d 100644
--- a/poison.h
+++ b/poison.h
@@ -39,7 +39,6 @@
 
 #pragma GCC poison CPU_INTERRUPT_HARD
 #pragma GCC poison CPU_INTERRUPT_EXITTB
-#pragma GCC poison CPU_INTERRUPT_TIMER
 #pragma GCC poison CPU_INTERRUPT_FIQ
 #pragma GCC poison CPU_INTERRUPT_HALT
 #pragma GCC poison CPU_INTERRUPT_SMI
-- 
1.7.4.4

[Qemu-devel] [PATCH 6/8] target-arm: Privatize CPU_INTERRUPT_FIQ.

[Richard Henderson]

This interrupt name was only used by the ARM port.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cpu-all.h        |    1 -
 poison.h         |    1 -
 target-arm/cpu.h |    4 ++++
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/cpu-all.h b/cpu-all.h
index a30943f..b1305db 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -828,7 +828,6 @@ extern CPUState *cpu_single_env;
 
 /* Temporary remapping from the generic names back to the previous
    cpu-specific names.  These will be moved to target-foo/cpu.h next.  */
-#define CPU_INTERRUPT_FIQ         CPU_INTERRUPT_TGT_EXT_1
 #define CPU_INTERRUPT_SMI         CPU_INTERRUPT_TGT_EXT_2
 #define CPU_INTERRUPT_VIRQ        CPU_INTERRUPT_TGT_INT_0
 #define CPU_INTERRUPT_NMI         CPU_INTERRUPT_TGT_EXT_3
diff --git a/poison.h b/poison.h
index 369d82d..787f8e9 100644
--- a/poison.h
+++ b/poison.h
@@ -39,7 +39,6 @@
 
 #pragma GCC poison CPU_INTERRUPT_HARD
 #pragma GCC poison CPU_INTERRUPT_EXITTB
-#pragma GCC poison CPU_INTERRUPT_FIQ
 #pragma GCC poison CPU_INTERRUPT_HALT
 #pragma GCC poison CPU_INTERRUPT_SMI
 #pragma GCC poison CPU_INTERRUPT_DEBUG
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index d5af644..01f5b57 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -55,6 +55,10 @@
 #define ARMV7M_EXCP_PENDSV  14
 #define ARMV7M_EXCP_SYSTICK 15
 
+/* ARM-specific interrupt pending bits.  */
+#define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
+
+
 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
                             int srcreg, int operand, uint32_t value);
 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
-- 
1.7.4.4

[Qemu-devel] [PATCH 7/8] target-i386: Privatize some i386-specific interrupt names.

[Richard Henderson]

SMI, VIRQ, INIT, SIPI, and MCE are all only used by the i386 port.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cpu-all.h         |    5 -----
 poison.h          |    2 --
 target-i386/cpu.h |    8 ++++++++
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/cpu-all.h b/cpu-all.h
index b1305db..39dfa46 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -828,12 +828,7 @@ extern CPUState *cpu_single_env;
 
 /* Temporary remapping from the generic names back to the previous
    cpu-specific names.  These will be moved to target-foo/cpu.h next.  */
-#define CPU_INTERRUPT_SMI         CPU_INTERRUPT_TGT_EXT_2
-#define CPU_INTERRUPT_VIRQ        CPU_INTERRUPT_TGT_INT_0
 #define CPU_INTERRUPT_NMI         CPU_INTERRUPT_TGT_EXT_3
-#define CPU_INTERRUPT_INIT        CPU_INTERRUPT_TGT_INT_1
-#define CPU_INTERRUPT_SIPI        CPU_INTERRUPT_TGT_INT_2
-#define CPU_INTERRUPT_MCE         CPU_INTERRUPT_TGT_EXT_4
 
 /* The set of all bits that should be masked when single-stepping.  */
 #define CPU_INTERRUPT_SSTEP_MASK \
diff --git a/poison.h b/poison.h
index 787f8e9..4fcf46d 100644
--- a/poison.h
+++ b/poison.h
@@ -40,9 +40,7 @@
 #pragma GCC poison CPU_INTERRUPT_HARD
 #pragma GCC poison CPU_INTERRUPT_EXITTB
 #pragma GCC poison CPU_INTERRUPT_HALT
-#pragma GCC poison CPU_INTERRUPT_SMI
 #pragma GCC poison CPU_INTERRUPT_DEBUG
-#pragma GCC poison CPU_INTERRUPT_VIRQ
 #pragma GCC poison CPU_INTERRUPT_NMI
 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index c7047d5..1fc421f 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -466,6 +466,14 @@
 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
                                  for syscall instruction */
 
+/* i386-specific interrupt pending bits.  */
+#define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
+#define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
+#define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
+#define CPU_INTERRUPT_INIT      CPU_INTERRUPT_TGT_INT_1
+#define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_2
+
+
 enum {
     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
-- 
1.7.4.4

[Qemu-devel] [PATCH 8/8] irq: Privatize CPU_INTERRUPT_NMI.

[Richard Henderson]

This interrupt name is used by i386, CRIS, and MicroBlaze.
Copy the name into each target.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cpu-all.h               |    4 ----
 poison.h                |    1 -
 target-cris/cpu.h       |    3 +++
 target-i386/cpu.h       |    1 +
 target-microblaze/cpu.h |    3 +++
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/cpu-all.h b/cpu-all.h
index 39dfa46..54df1d3 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -826,10 +826,6 @@ extern CPUState *cpu_single_env;
 
 /* First unused bit: 0x2000.  */
 
-/* Temporary remapping from the generic names back to the previous
-   cpu-specific names.  These will be moved to target-foo/cpu.h next.  */
-#define CPU_INTERRUPT_NMI         CPU_INTERRUPT_TGT_EXT_3
-
 /* The set of all bits that should be masked when single-stepping.  */
 #define CPU_INTERRUPT_SSTEP_MASK \
     (CPU_INTERRUPT_HARD          \
diff --git a/poison.h b/poison.h
index 4fcf46d..2b18232 100644
--- a/poison.h
+++ b/poison.h
@@ -41,7 +41,6 @@
 #pragma GCC poison CPU_INTERRUPT_EXITTB
 #pragma GCC poison CPU_INTERRUPT_HALT
 #pragma GCC poison CPU_INTERRUPT_DEBUG
-#pragma GCC poison CPU_INTERRUPT_NMI
 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_2
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index d908775..8686dba 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -36,6 +36,9 @@
 #define EXCP_IRQ        4
 #define EXCP_BREAK      5
 
+/* CRIS-specific interrupt pending bits.  */
+#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
+
 /* Register aliases. R0 - R15 */
 #define R_FP  8
 #define R_SP  14
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 1fc421f..715828f 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -468,6 +468,7 @@
 
 /* i386-specific interrupt pending bits.  */
 #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
+#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
 #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
 #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_TGT_INT_1
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 536222e..78fe14ff 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -41,6 +41,9 @@ struct CPUMBState;
 #define EXCP_HW_BREAK   5
 #define EXCP_HW_EXCP    6
 
+/* MicroBlaze-specific interrupt pending bits.  */
+#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
+
 /* Register aliases. R0 - R15 */
 #define R_SP     1
 #define SR_PC    0
-- 
1.7.4.4

Re: [Qemu-devel] [PATCH 0/8] cpu interrupt cleanup, v2

[Richard Henderson]

Ping?

On 05/04/2011 01:34 PM, Richard Henderson wrote:
> v1->v2
>   Rebase vs HEAD (d2d979c)
>   Cleanup whitespace errors.
> 
> 
> r~
> 
> Richard Henderson (8):
>   irq: Introduce CPU_INTERRUPT_TGT_* defines.
>   irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK.
>   target-mips: Do not check CPU_INTERRUPT_TIMER.
>   target-sparc: Do not check CPU_INTERRUPT_TIMER.
>   irq: Remove CPU_INTERRUPT_TIMER.
>   target-arm: Privatize CPU_INTERRUPT_FIQ.
>   target-i386: Privatize some i386-specific interrupt names.
>   irq: Privatize CPU_INTERRUPT_NMI.
> 
>  cpu-all.h               |   60 +++++++++++++++++++++++++++++++++++++---------
>  cpu-exec.c              |    8 +-----
>  poison.h                |   13 ++++++----
>  target-arm/cpu.h        |    4 +++
>  target-cris/cpu.h       |    3 ++
>  target-i386/cpu.h       |    9 +++++++
>  target-microblaze/cpu.h |    3 ++
>  target-mips/exec.h      |    4 ---
>  8 files changed, 76 insertions(+), 28 deletions(-)
> 

Re: [Qemu-devel] [PATCH 0/8] cpu interrupt cleanup, v2

[Blue Swirl]

Thanks, applied.

On Sun, May 8, 2011 at 7:50 PM, Richard Henderson <rth@twiddle.net> wrote:
> Ping?
>
> On 05/04/2011 01:34 PM, Richard Henderson wrote:
>> v1->v2
>>   Rebase vs HEAD (d2d979c)
>>   Cleanup whitespace errors.
>>
>>
>> r~
>>
>> Richard Henderson (8):
>>   irq: Introduce CPU_INTERRUPT_TGT_* defines.
>>   irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK.
>>   target-mips: Do not check CPU_INTERRUPT_TIMER.
>>   target-sparc: Do not check CPU_INTERRUPT_TIMER.
>>   irq: Remove CPU_INTERRUPT_TIMER.
>>   target-arm: Privatize CPU_INTERRUPT_FIQ.
>>   target-i386: Privatize some i386-specific interrupt names.
>>   irq: Privatize CPU_INTERRUPT_NMI.
>>
>>  cpu-all.h               |   60 +++++++++++++++++++++++++++++++++++++---------
>>  cpu-exec.c              |    8 +-----
>>  poison.h                |   13 ++++++----
>>  target-arm/cpu.h        |    4 +++
>>  target-cris/cpu.h       |    3 ++
>>  target-i386/cpu.h       |    9 +++++++
>>  target-microblaze/cpu.h |    3 ++
>>  target-mips/exec.h      |    4 ---
>>  8 files changed, 76 insertions(+), 28 deletions(-)
>>
>
>

[Qemu-devel] [PATCH 0/8] cpu interrupt cleanup

[Richard Henderson]

Blue Swirl pointed out that CPU_INTERRUPT_TIMER was unused,
and should therefore be remove.  This is a logical extension
of that, making all target specific cpu interrupts really be
private to the target.

This will allow new ports to define external cpu interrupts
as needed without having to modify generic code.


r~


Richard Henderson (8):
  irq: Introduce CPU_INTERRUPT_TGT_* defines.
  irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK.
  target-mips: Do not check CPU_INTERRUPT_TIMER.
  target-sparc: Do not check CPU_INTERRUPT_TIMER.
  irq: Remove CPU_INTERRUPT_TIMER.
  target-arm: Privatize CPU_INTERRUPT_FIQ.
  target-i386: Privatize some i386-specific interrupt names.
  irq: Privatize CPU_INTERRUPT_NMI.

 cpu-all.h               |   60 +++++++++++++++++++++++++++++++++++++---------
 cpu-exec.c              |    8 +-----
 poison.h                |   13 ++++++----
 target-arm/cpu.h        |    4 +++
 target-cris/cpu.h       |    3 ++
 target-i386/cpu.h       |    9 +++++++
 target-microblaze/cpu.h |    3 ++
 target-mips/exec.h      |    4 ---
 8 files changed, 76 insertions(+), 28 deletions(-)

-- 
1.7.4.4

[Qemu-devel] [PATCH 2/8] irq: Introduce and use CPU_INTERRUPT_SSTEP_MASK.

[Richard Henderson]

This mask contains all of the bits that should be ignored while single
stepping in the debugger.  The mask contains 2 bits that are not currently
cleared, but are also never set.  The bits are included in the mask for
consistency in handling of the CPU_INTERRUPT_TGT_EXT_N bits.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cpu-all.h  |    8 ++++++++
 cpu-exec.c |    5 +----
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/cpu-all.h b/cpu-all.h
index 8c3222e..f813ef8 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -837,6 +837,14 @@ extern CPUState *cpu_single_env;
 #define CPU_INTERRUPT_SIPI	CPU_INTERRUPT_TGT_INT_2
 #define CPU_INTERRUPT_MCE	CPU_INTERRUPT_TGT_EXT_4
 
+/* The set of all bits that should be masked when single-stepping.  */
+#define CPU_INTERRUPT_SSTEP_MASK \
+    (CPU_INTERRUPT_HARD          \
+     | CPU_INTERRUPT_TGT_EXT_0   \
+     | CPU_INTERRUPT_TGT_EXT_1   \
+     | CPU_INTERRUPT_TGT_EXT_2   \
+     | CPU_INTERRUPT_TGT_EXT_3   \
+     | CPU_INTERRUPT_TGT_EXT_4)
 
 void cpu_interrupt(CPUState *s, int mask);
 void cpu_reset_interrupt(CPUState *env, int mask);
diff --git a/cpu-exec.c b/cpu-exec.c
index 395cd8c..5b42b25 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -360,10 +360,7 @@ int cpu_exec(CPUState *env1)
                 if (unlikely(interrupt_request)) {
                     if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
                         /* Mask out external interrupts for this step. */
-                        interrupt_request &= ~(CPU_INTERRUPT_HARD |
-                                               CPU_INTERRUPT_FIQ |
-                                               CPU_INTERRUPT_SMI |
-                                               CPU_INTERRUPT_NMI);
+                        interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
                     }
                     if (interrupt_request & CPU_INTERRUPT_DEBUG) {
                         env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
-- 
1.7.4.4