From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:40592) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIKtu-0000Yp-Oa for qemu-devel@nongnu.org; Fri, 06 May 2011 09:16:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QIKtt-0007Si-OV for qemu-devel@nongnu.org; Fri, 06 May 2011 09:16:58 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:36404) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIKtt-0007Sc-Db for qemu-devel@nongnu.org; Fri, 06 May 2011 09:16:57 -0400 From: Peter Maydell Date: Fri, 6 May 2011 13:48:15 +0100 Message-Id: <1304686095-30265-8-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1304686095-30265-1-git-send-email-peter.maydell@linaro.org> References: <1304686095-30265-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 7/7] target-arm: Signal Underflow when denormal flushed to zero on output List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org On ARM the architecture mandates that when an output denormal is flushed to zero we must set the FPSCR UFC (underflow) bit, so map softfloat's float_flag_output_denormal accordingly. Signed-off-by: Peter Maydell --- target-arm/helper.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index de00468..149fc82 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2355,7 +2355,7 @@ static inline int vfp_exceptbits_from_host(int host_bits) target_bits |= 2; if (host_bits & float_flag_overflow) target_bits |= 4; - if (host_bits & float_flag_underflow) + if (host_bits & (float_flag_underflow | float_flag_output_denormal)) target_bits |= 8; if (host_bits & float_flag_inexact) target_bits |= 0x10; -- 1.7.1