From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:52051) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJ6Ug-0006MF-0X for qemu-devel@nongnu.org; Sun, 08 May 2011 12:06:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QJ6UZ-0007TY-OP for qemu-devel@nongnu.org; Sun, 08 May 2011 12:06:05 -0400 Received: from mtagate1.uk.ibm.com ([194.196.100.161]:38417) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJ6UZ-0007SI-Fe for qemu-devel@nongnu.org; Sun, 08 May 2011 12:05:59 -0400 Received: from d06nrmr1707.portsmouth.uk.ibm.com (d06nrmr1707.portsmouth.uk.ibm.com [9.149.39.225]) by mtagate1.uk.ibm.com (8.13.1/8.13.1) with ESMTP id p48G5vJN023760 for ; Sun, 8 May 2011 16:05:57 GMT Received: from d06av11.portsmouth.uk.ibm.com (d06av11.portsmouth.uk.ibm.com [9.149.37.252]) by d06nrmr1707.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p48G7DJN2293800 for ; Sun, 8 May 2011 17:07:13 +0100 Received: from d06av11.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av11.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p48G5vde021593 for ; Sun, 8 May 2011 10:05:57 -0600 From: Stefan Hajnoczi Date: Sun, 8 May 2011 17:05:01 +0100 Message-Id: <1304870719-20885-7-git-send-email-stefanha@linux.vnet.ibm.com> In-Reply-To: <1304870719-20885-1-git-send-email-stefanha@linux.vnet.ibm.com> References: <1304870719-20885-1-git-send-email-stefanha@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 06/24] Fix typo in comment (auxilliary -> auxiliary) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org, Stefan Hajnoczi From: Stefan Weil Signed-off-by: Stefan Weil Signed-off-by: Stefan Hajnoczi --- hw/pci_regs.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/hw/pci_regs.h b/hw/pci_regs.h index dd0bed4..5a5ab89 100644 --- a/hw/pci_regs.h +++ b/hw/pci_regs.h @@ -223,7 +223,7 @@ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ -#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ +#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ -- 1.7.4.4