From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:38313) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY6b-0003OZ-NU for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QJY6a-0006FU-Uv for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:05 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:48729) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY6a-0006A3-Rc for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:04 -0400 Received: by mail-iy0-f173.google.com with SMTP id 10so5564538iym.4 for ; Mon, 09 May 2011 14:35:04 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 9 May 2011 14:34:23 -0700 Message-Id: <1304976889-29675-10-git-send-email-rth@twiddle.net> In-Reply-To: <1304976889-29675-1-git-send-email-rth@twiddle.net> References: <1304976889-29675-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 09/35] target-alpha: Cleanup MMU modes. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Don't bother including executive and supervisor modes. Signed-off-by: Richard Henderson --- target-alpha/cpu.h | 36 ++++++++++++++++++++++++++++-------- 1 files changed, 28 insertions(+), 8 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 1fc21dc..bdd396c 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -192,6 +192,33 @@ enum { #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK) +/* MMU modes definitions */ + +/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user. + The Unix PALcode only exposes the kernel and user modes; presumably + executive and supervisor are used by VMS. + + PALcode itself uses physical mode for code and kernel mode for data; + there are PALmode instructions that can access data via physical mode + or via an os-installed "alternate mode", which is one of the 4 above. + + QEMU does not currently properly distinguish between code/data when + looking up addresses. To avoid having to address this issue, our + emulated PALcode will cheat and use the KSEG mapping for its code+data + rather than physical addresses. + + Moreover, we're only emulating Unix PALcode, and not attempting VMS. + + All of which allows us to drop all but kernel and user modes. + Elide the unused MMU modes to save space. */ + +#define NB_MMU_MODES 2 + +#define MMU_MODE0_SUFFIX _kernel +#define MMU_MODE1_SUFFIX _user +#define MMU_KERNEL_IDX 0 +#define MMU_USER_IDX 1 + typedef struct CPUAlphaState CPUAlphaState; struct CPUAlphaState { @@ -246,16 +273,9 @@ struct CPUAlphaState { #define cpu_gen_code cpu_alpha_gen_code #define cpu_signal_handler cpu_alpha_signal_handler -/* MMU modes definitions */ -#define NB_MMU_MODES 4 -#define MMU_MODE0_SUFFIX _kernel -#define MMU_MODE1_SUFFIX _executive -#define MMU_MODE2_SUFFIX _supervisor -#define MMU_MODE3_SUFFIX _user -#define MMU_USER_IDX 3 static inline int cpu_mmu_index (CPUState *env) { - return (env->ps >> 3) & 3; + return (env->ps >> 3) & 1; } #include "cpu-all.h" -- 1.7.4.4