From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:50525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSph-0006Dy-C2 for qemu-devel@nongnu.org; Tue, 17 May 2011 18:33:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QMSpg-0000OC-05 for qemu-devel@nongnu.org; Tue, 17 May 2011 18:33:41 -0400 Received: from mail-ew0-f45.google.com ([209.85.215.45]:37210) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSpf-0000KZ-RP for qemu-devel@nongnu.org; Tue, 17 May 2011 18:33:39 -0400 Received: by mail-ew0-f45.google.com with SMTP id 24so340090ewy.4 for ; Tue, 17 May 2011 15:33:39 -0700 (PDT) From: Max Filippov Date: Wed, 18 May 2011 02:32:35 +0400 Message-Id: <1305671572-5899-10-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> References: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH 09/26] target-xtensa: add special and user registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Max Filippov Special Registers hold the majority of the state added to the processor by the options. See ISA, 5.3 for details. User Registers hold state added in support of designer's TIE and in some cases of options that Tensilica provides. See ISA, 5.4 for details. Only registers mapped in sregnames or uregnames are considered valid. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 7 ++++++ target-xtensa/translate.c | 47 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index d8cd923..0b40fa8 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -99,6 +99,12 @@ enum { XTENSA_OPTIN_TRACE_PORT, }; +enum { + THREADPTR = 231, + FCR = 232, + FSR = 233, +}; + typedef struct XtensaConfig { const char *name; uint64_t options; @@ -109,6 +115,7 @@ typedef struct CPUXtensaState { uint32_t regs[16]; uint32_t pc; uint32_t sregs[256]; + uint32_t uregs[256]; CPU_COMMON } CPUXtensaState; diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 0a43ec0..2fcd36d 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -52,9 +52,20 @@ typedef struct DisasContext { static TCGv_ptr cpu_env; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; +static TCGv_i32 cpu_SR[256]; +static TCGv_i32 cpu_UR[256]; #include "gen-icount.h" +static const char * const sregnames[256] = { +}; + +static const char * const uregnames[256] = { + [THREADPTR] = "THREADPTR", + [FCR] = "FCR", + [FSR] = "FSR", +}; + void xtensa_translate_init(void) { static const char * const regnames[] = { @@ -74,6 +85,22 @@ void xtensa_translate_init(void) offsetof(CPUState, regs[i]), regnames[i]); } + + for (i = 0; i < 256; ++i) { + if (sregnames[i]) { + cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, sregs[i]), + sregnames[i]); + } + } + + for (i = 0; i < 256; ++i) { + if (uregnames[i]) { + cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, uregs[i]), + uregnames[i]); + } + } } static inline int option_enabled(DisasContext *dc, int opt) @@ -777,9 +804,25 @@ void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, int flags) { - int i; + int i, j; + + cpu_fprintf(f, "PC=%08x\n\n", env->pc); + + for (i = j = 0; i < 256; ++i) + if (sregnames[i]) { + cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i], + (j++ % 4) == 3 ? '\n' : ' '); + } + + cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); + + for (i = j = 0; i < 256; ++i) + if (uregnames[i]) { + cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i], + (j++ % 4) == 3 ? '\n' : ' '); + } - cpu_fprintf(f, "PC=%08x\n", env->pc); + cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); for (i = 0; i < 16; ++i) cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i], -- 1.7.3.4