From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:50763) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSqA-00079u-QE for qemu-devel@nongnu.org; Tue, 17 May 2011 18:34:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QMSq9-0000TT-Su for qemu-devel@nongnu.org; Tue, 17 May 2011 18:34:10 -0400 Received: from mail-ey0-f173.google.com ([209.85.215.173]:53774) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSq9-0000MT-O5 for qemu-devel@nongnu.org; Tue, 17 May 2011 18:34:09 -0400 Received: by mail-ey0-f173.google.com with SMTP id 6so338540eyb.4 for ; Tue, 17 May 2011 15:34:09 -0700 (PDT) From: Max Filippov Date: Wed, 18 May 2011 02:32:43 +0400 Message-Id: <1305671572-5899-18-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> References: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> Subject: [Qemu-devel] [PATCH 17/26] target-xtensa: implement RST2 group (32 bit mul/div/rem) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Max Filippov Signed-off-by: Max Filippov --- target-xtensa/translate.c | 60 ++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 59 insertions(+), 1 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 7deda1b..8933e5a 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -854,7 +854,65 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 2: /*RST2*/ - TBD(); + if (_OP2 >= 12) { + HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV); + int label = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label); + gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); + gen_set_label(label); + } + + switch (_OP2) { + case 8: /*MULLi*/ + HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); + tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); + break; + + case 10: /*MULUHi*/ + case 11: /*MULSHi*/ + HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); + { + TCGv_i64 r = tcg_temp_new_i64(); + TCGv_i64 s = tcg_temp_new_i64(); + TCGv_i64 t = tcg_temp_new_i64(); + + if (_OP2 == 10) { + tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]); + tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]); + } else { + tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]); + tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]); + } + tcg_gen_mul_i64(r, s, t); + tcg_gen_shri_i64(r, r, 32); + tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r); + + tcg_temp_free_i64(r); + tcg_temp_free_i64(s); + tcg_temp_free_i64(t); + } + break; + + case 12: /*QUOUi*/ + tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); + break; + + case 13: /*QUOSi*/ + tcg_gen_div_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); + break; + + case 14: /*REMUi*/ + tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); + break; + + case 15: /*REMSi*/ + tcg_gen_rem_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); + break; + + default: /*reserved*/ + RESERVED(); + break; + } break; case 3: /*RST3*/ -- 1.7.3.4