From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44704) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QOGiO-0006Hi-TH for qemu-devel@nongnu.org; Sun, 22 May 2011 18:01:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QOGiM-0006jJ-8x for qemu-devel@nongnu.org; Sun, 22 May 2011 18:01:36 -0400 Received: from mtagate2.uk.ibm.com ([194.196.100.162]:37277) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QOGiL-0006ix-Rm for qemu-devel@nongnu.org; Sun, 22 May 2011 18:01:34 -0400 Received: from d06nrmr1307.portsmouth.uk.ibm.com (d06nrmr1307.portsmouth.uk.ibm.com [9.149.38.129]) by mtagate2.uk.ibm.com (8.13.1/8.13.1) with ESMTP id p4MM1WfI006652 for ; Sun, 22 May 2011 22:01:32 GMT Received: from d06av05.portsmouth.uk.ibm.com (d06av05.portsmouth.uk.ibm.com [9.149.37.229]) by d06nrmr1307.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p4MM1RJK2412730 for ; Sun, 22 May 2011 23:01:32 +0100 Received: from d06av05.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av05.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p4MM1QpV011944 for ; Sun, 22 May 2011 16:01:26 -0600 From: Stefan Hajnoczi Date: Sun, 22 May 2011 23:01:17 +0100 Message-Id: <1306101677-26631-5-git-send-email-stefanha@linux.vnet.ibm.com> In-Reply-To: <1306101677-26631-1-git-send-email-stefanha@linux.vnet.ibm.com> References: <1306101677-26631-1-git-send-email-stefanha@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 4/4] Fix typos in comments (chek -> check) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Anthony Liguori , Stefan Hajnoczi From: Stefan Weil Signed-off-by: Stefan Weil Signed-off-by: Stefan Hajnoczi --- exec.c | 2 +- target-ppc/STATUS | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/exec.c b/exec.c index a6df2d6..563e974 100644 --- a/exec.c +++ b/exec.c @@ -2061,7 +2061,7 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, /* we modify the TLB cache so that the dirty bit will be set again when accessing the range */ start1 = (unsigned long)qemu_safe_ram_ptr(start); - /* Chek that we don't span multiple blocks - this breaks the + /* Check that we don't span multiple blocks - this breaks the address comparisons below. */ if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1 != (end - 1) - start) { diff --git a/target-ppc/STATUS b/target-ppc/STATUS index 32e7ffa..c8e9018 100644 --- a/target-ppc/STATUS +++ b/target-ppc/STATUS @@ -11,7 +11,7 @@ INSN: instruction set. SPR: special purpose registers set OK => all SPR registered (but some may be fake) KO => some SPR are missing or should be removed - ? => uncheked + ? => unchecked MSR: MSR bits definitions OK => all MSR bits properly defined KO => MSR definition is incorrect -- 1.7.4.4