From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:42790) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObkd-0005G7-77 for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QObkc-0008MN-82 for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:19 -0400 Received: from mail-yi0-f45.google.com ([209.85.218.45]:61626) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObkc-0008MB-5D for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:18 -0400 Received: by yib19 with SMTP id 19so2718519yib.4 for ; Mon, 23 May 2011 13:29:17 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 23 May 2011 13:28:34 -0700 Message-Id: <1306182526-12081-15-git-send-email-rth@twiddle.net> In-Reply-To: <1306182526-12081-1-git-send-email-rth@twiddle.net> References: <1306182526-12081-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 14/26] target-alpha: Add various symbolic constants. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The EXC_M_* constants were being set for the EV6, not as set for the Unix kernel entry point. Use PS_USER_MODE instead of hard-coding access to the PS register. Signed-off-by: Richard Henderson --- target-alpha/cpu.h | 56 +++++++++++++++++++++++++++++++++++---------- target-alpha/translate.c | 2 +- 2 files changed, 44 insertions(+), 14 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 01e3741..4407b32 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -274,11 +274,6 @@ struct CPUAlphaState { #define cpu_gen_code cpu_alpha_gen_code #define cpu_signal_handler cpu_alpha_signal_handler -static inline int cpu_mmu_index (CPUState *env) -{ - return (env->ps >> 3) & 1; -} - #include "cpu-all.h" enum { @@ -305,14 +300,49 @@ enum { EXCP_STQ_C, }; -/* Arithmetic exception */ -#define EXC_M_IOV (1<<16) /* Integer Overflow */ -#define EXC_M_INE (1<<15) /* Inexact result */ -#define EXC_M_UNF (1<<14) /* Underflow */ -#define EXC_M_FOV (1<<13) /* Overflow */ -#define EXC_M_DZE (1<<12) /* Division by zero */ -#define EXC_M_INV (1<<11) /* Invalid operation */ -#define EXC_M_SWC (1<<10) /* Software completion */ +/* Hardware interrupt (entInt) constants. */ +enum { + INT_K_IP, + INT_K_CLK, + INT_K_MCHK, + INT_K_DEV, + INT_K_PERF, +}; + +/* Memory management (entMM) constants. */ +enum { + MM_K_TNV, + MM_K_ACV, + MM_K_FOR, + MM_K_FOE, + MM_K_FOW +}; + +/* Arithmetic exception (entArith) constants. */ +enum { + EXC_M_SWC = 1, /* Software completion */ + EXC_M_INV = 2, /* Invalid operation */ + EXC_M_DZE = 4, /* Division by zero */ + EXC_M_FOV = 8, /* Overflow */ + EXC_M_UNF = 16, /* Underflow */ + EXC_M_INE = 32, /* Inexact result */ + EXC_M_IOV = 64 /* Integer Overflow */ +}; + +/* Processor status constants. */ +enum { + /* Low 3 bits are interrupt mask level. */ + PS_INT_MASK = 7, + + /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes; + The Unix PALcode only uses bit 4. */ + PS_USER_MODE = 8 +}; + +static inline int cpu_mmu_index(CPUState *env) +{ + return (env->ps & PS_USER_MODE) != 0; +} enum { IR_V0 = 0, diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 5f40d34..2f3c637 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3269,7 +3269,7 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model) env->amask = amask; #if defined (CONFIG_USER_ONLY) - env->ps = 1 << 3; + env->ps = PS_USER_MODE; cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD | FPCR_UNFD | FPCR_INED | FPCR_DNOD)); #endif -- 1.7.4.4