From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:42846) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObkh-0005Nv-Ji for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QObkg-0008NP-4j for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:23 -0400 Received: from mail-yw0-f45.google.com ([209.85.213.45]:33315) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObkf-0008Iw-VK for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:22 -0400 Received: by mail-yw0-f45.google.com with SMTP id 41so2717843ywl.4 for ; Mon, 23 May 2011 13:29:21 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 23 May 2011 13:28:38 -0700 Message-Id: <1306182526-12081-19-git-send-email-rth@twiddle.net> In-Reply-To: <1306182526-12081-1-git-send-email-rth@twiddle.net> References: <1306182526-12081-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 18/26] target-alpha: Swap shadow registers moving to/from PALmode. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Richard Henderson --- target-alpha/cpu.h | 1 + target-alpha/helper.c | 37 ++++++++++++++++++++++++++++++++++++- target-alpha/op_helper.c | 5 ++++- 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index d1ef04d..c1546f8 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -416,6 +416,7 @@ void do_interrupt (CPUState *env); uint64_t cpu_alpha_load_fpcr (CPUState *env); void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); +extern void swap_shadow_regs(CPUState *env); static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, target_ulong *cs_base, int *flags) diff --git a/target-alpha/helper.c b/target-alpha/helper.c index a49f632..4f706f2 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -168,6 +168,38 @@ int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, return 1; } #else +void swap_shadow_regs(CPUState *env) +{ + uint64_t i0, i1, i2, i3, i4, i5, i6, i7; + + i0 = env->ir[8]; + i1 = env->ir[9]; + i2 = env->ir[10]; + i3 = env->ir[11]; + i4 = env->ir[12]; + i5 = env->ir[13]; + i6 = env->ir[14]; + i7 = env->ir[25]; + + env->ir[8] = env->shadow[0]; + env->ir[9] = env->shadow[1]; + env->ir[10] = env->shadow[2]; + env->ir[11] = env->shadow[3]; + env->ir[12] = env->shadow[4]; + env->ir[13] = env->shadow[5]; + env->ir[14] = env->shadow[6]; + env->ir[25] = env->shadow[7]; + + env->shadow[0] = i0; + env->shadow[1] = i1; + env->shadow[2] = i2; + env->shadow[3] = i3; + env->shadow[4] = i4; + env->shadow[5] = i5; + env->shadow[6] = i6; + env->shadow[7] = i7; +} + target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) { return -1; @@ -290,7 +322,10 @@ void do_interrupt (CPUState *env) env->pc = env->palbr + i; /* Switch to PALmode. */ - env->pal_mode = 1; + if (!env->pal_mode) { + env->pal_mode = 1; + swap_shadow_regs(env); + } #endif /* !USER_ONLY */ } diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index fc5020a..03b5091 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1189,9 +1189,12 @@ uint64_t helper_cvtqg (uint64_t a) void helper_hw_ret (uint64_t a) { env->pc = a & ~3; - env->pal_mode = a & 1; env->intr_flag = 0; env->lock_addr = -1; + if ((a & 1) == 0) { + env->pal_mode = 0; + swap_shadow_regs(env); + } } #endif -- 1.7.4.4