From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 21/26] target-alpha: Implement more CALL_PAL values inline.
Date: Mon, 23 May 2011 13:28:41 -0700 [thread overview]
Message-ID: <1306182526-12081-22-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1306182526-12081-1-git-send-email-rth@twiddle.net>
In particular, SWPIPL is used quite a lot by the Linux kernel.
Doing this inline makes it significantly easier to step through
without the debugger getting confused by the mode switch.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-alpha/translate.c | 140 +++++++++++++++++++++++++++++++++++-----------
1 files changed, 108 insertions(+), 32 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index a6c6bca..e664d62 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -85,8 +85,10 @@ static TCGv cpu_pc;
static TCGv cpu_lock_addr;
static TCGv cpu_lock_st_addr;
static TCGv cpu_lock_value;
-#ifdef CONFIG_USER_ONLY
-static TCGv cpu_uniq;
+static TCGv cpu_unique;
+#ifndef CONFIG_USER_ONLY
+static TCGv cpu_sysval;
+static TCGv cpu_usp;
#endif
/* register names */
@@ -131,9 +133,13 @@ static void alpha_translate_init(void)
offsetof(CPUState, lock_value),
"lock_value");
-#ifdef CONFIG_USER_ONLY
- cpu_uniq = tcg_global_mem_new_i64(TCG_AREG0,
- offsetof(CPUState, unique), "uniq");
+ cpu_unique = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUState, unique), "unique");
+#ifndef CONFIG_USER_ONLY
+ cpu_sysval = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUState, sysval), "sysval");
+ cpu_usp = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUState, usp), "usp");
#endif
/* register helpers */
@@ -1464,6 +1470,101 @@ static void gen_rx(int ra, int set)
tcg_temp_free_i32(tmp);
}
+static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
+{
+ /* We're emulating OSF/1 PALcode. Many of these are trivial access
+ to internal cpu registers. */
+
+ /* Unprivileged PAL call */
+ if (palcode >= 0x80 && palcode < 0xC0) {
+ switch (palcode) {
+ case 0x86:
+ /* IMB */
+ /* No-op inside QEMU. */
+ break;
+ case 0x9E:
+ /* RDUNIQUE */
+ tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_unique);
+ break;
+ case 0x9F:
+ /* WRUNIQUE */
+ tcg_gen_mov_i64(cpu_unique, cpu_ir[IR_A0]);
+ break;
+ default:
+ return gen_excp(ctx, EXCP_CALL_PAL, palcode & 0xbf);
+ }
+ return NO_EXIT;
+ }
+
+#ifndef CONFIG_USER_ONLY
+ /* Privileged PAL code */
+ if (palcode < 0x40 && (ctx->tb->flags & TB_FLAGS_USER_MODE) == 0) {
+ switch (palcode) {
+ case 0x01:
+ /* CFLUSH */
+ /* No-op inside QEMU. */
+ break;
+ case 0x02:
+ /* DRAINA */
+ /* No-op inside QEMU. */
+ break;
+ case 0x2D:
+ /* WRVPTPTR */
+ tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUState, vptptr));
+ break;
+ case 0x31:
+ /* WRVAL */
+ tcg_gen_mov_i64(cpu_sysval, cpu_ir[IR_A0]);
+ break;
+ case 0x32:
+ /* RDVAL */
+ tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_sysval);
+ break;
+
+ case 0x35: {
+ /* SWPIPL */
+ TCGv tmp;
+
+ /* Note that we already know we're in kernel mode, so we know
+ that PS only contains the 3 IPL bits. */
+ tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps));
+
+ /* But make sure and store only the 3 IPL bits from the user. */
+ tmp = tcg_temp_new();
+ tcg_gen_andi_i64(tmp, cpu_ir[IR_A0], PS_INT_MASK);
+ tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUState, ps));
+ tcg_temp_free(tmp);
+ break;
+ }
+
+ case 0x36:
+ /* RDPS */
+ tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps));
+ break;
+ case 0x38:
+ /* WRUSP */
+ tcg_gen_mov_i64(cpu_usp, cpu_ir[IR_A0]);
+ break;
+ case 0x3A:
+ /* RDUSP */
+ tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_usp);
+ break;
+ case 0x3C:
+ /* WHAMI */
+ tcg_gen_ld32s_i64(cpu_ir[IR_V0], cpu_env,
+ offsetof(CPUState, cpu_index));
+ break;
+
+ default:
+ return gen_excp(ctx, EXCP_CALL_PAL, palcode & 0x3f);
+ }
+ return NO_EXIT;
+ }
+#endif
+
+ return gen_invalid(ctx);
+}
+
#ifndef CONFIG_USER_ONLY
#define PR_BYTE 0x100000
@@ -1582,33 +1683,8 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
switch (opc) {
case 0x00:
/* CALL_PAL */
-#ifdef CONFIG_USER_ONLY
- if (palcode == 0x9E) {
- /* RDUNIQUE */
- tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_uniq);
- break;
- } else if (palcode == 0x9F) {
- /* WRUNIQUE */
- tcg_gen_mov_i64(cpu_uniq, cpu_ir[IR_A0]);
- break;
- }
-#endif
- if (palcode >= 0x80 && palcode < 0xC0) {
- /* Unprivileged PAL call */
- ret = gen_excp(ctx, EXCP_CALL_PAL, palcode & 0xBF);
- break;
- }
-#ifndef CONFIG_USER_ONLY
- if (palcode < 0x40) {
- /* Privileged PAL code */
- if (ctx->mem_idx != MMU_KERNEL_IDX) {
- goto invalid_opc;
- }
- ret = gen_excp(ctx, EXCP_CALL_PAL, palcode & 0x3F);
- }
-#endif
- /* Invalid PAL call */
- goto invalid_opc;
+ ret = gen_call_pal(ctx, palcode);
+ break;
case 0x01:
/* OPC01 */
goto invalid_opc;
--
1.7.4.4
next prev parent reply other threads:[~2011-05-23 20:29 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-23 20:28 [Qemu-devel] [PULL 00/26] Alpha system emulation, v5 Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 01/26] target-alpha: Claim ownership Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 02/26] target-alpha: Disassemble EV6 PALcode instructions Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 03/26] target-alpha: Single-step properly across branches Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 04/26] target-alpha: Remove partial support for palcode emulation Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 05/26] target-alpha: Fix translation of PALmode memory insns Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 06/26] target-alpha: Fix system store_conditional Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 07/26] target-alpha: Cleanup MMU modes Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 08/26] target-alpha: Merge HW_REI and HW_RET implementations Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 09/26] target-alpha: Rationalize internal processor registers Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 10/26] target-alpha: Enable the alpha-softmmu target Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 11/26] target-alpha: Tidy exception constants Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 12/26] target-alpha: Tidy up arithmetic exceptions Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 13/26] target-alpha: Use do_restore_state for " Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 14/26] target-alpha: Add various symbolic constants Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 15/26] target-alpha: Use kernel mmu_idx for pal_mode Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 16/26] target-alpha: Add IPRs to be used by the emulation PALcode Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 17/26] target-alpha: Implement do_interrupt for system mode Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 18/26] target-alpha: Swap shadow registers moving to/from PALmode Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 19/26] target-alpha: All ISA checks to use TB->FLAGS Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 20/26] target-alpha: Disable interrupts properly Richard Henderson
2011-05-23 20:28 ` Richard Henderson [this message]
2011-05-23 20:28 ` [Qemu-devel] [PATCH 22/26] target-alpha: Implement cpu_alpha_handle_mmu_fault for system mode Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 23/26] target-alpha: Remap PIO space for 43-bit KSEG for EV6 Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 24/26] target-alpha: Trap for unassigned and unaligned addresses Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 25/26] target-alpha: Use a fixed frequency for the RPCC in system mode Richard Henderson
2011-05-23 20:28 ` [Qemu-devel] [PATCH 26/26] target-alpha: Implement TLB flush primitives Richard Henderson
2011-05-27 19:55 ` [Qemu-devel] [PULL 00/26] Alpha system emulation, v5 Richard Henderson
2011-06-02 14:56 ` Richard Henderson
2011-06-08 19:10 ` Richard Henderson
2011-06-10 20:32 ` Edgar E. Iglesias
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