From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:50024) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRaOc-00051w-Uu for qemu-devel@nongnu.org; Tue, 31 May 2011 21:38:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QRaOb-0007HB-48 for qemu-devel@nongnu.org; Tue, 31 May 2011 21:38:54 -0400 Received: from mail-bw0-f45.google.com ([209.85.214.45]:36086) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRaOa-0007GK-RO for qemu-devel@nongnu.org; Tue, 31 May 2011 21:38:53 -0400 Received: by mail-bw0-f45.google.com with SMTP id 16so4438176bwz.4 for ; Tue, 31 May 2011 18:38:52 -0700 (PDT) Sender: Eduard - Gabriel Munteanu From: Eduard - Gabriel Munteanu Date: Wed, 1 Jun 2011 04:38:24 +0300 Message-Id: <1306892315-7306-3-git-send-email-eduard.munteanu@linux360.ro> In-Reply-To: <1306892315-7306-1-git-send-email-eduard.munteanu@linux360.ro> References: <1306892315-7306-1-git-send-email-eduard.munteanu@linux360.ro> Subject: [Qemu-devel] [RFC PATCH 02/13] pci: add IOMMU support via the generic DMA layer List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mst@redhat.com Cc: aliguori@us.ibm.com, david@gibson.dropbear.id.au, kvm@vger.kernel.org, rth@twiddle.net, aik@ozlabs.ru, joro@8bytes.org, seabios@seabios.org, qemu-devel@nongnu.org, agraf@suse.de, blauwirbel@gmail.com, yamahata@valinux.co.jp, kevin@koconnor.net, avi@redhat.com, Eduard - Gabriel Munteanu , dwg@au1.ibm.com, paul@codesourcery.com IOMMUs can now be hooked onto the PCI bus. This makes use of the generic DMA layer. Signed-off-by: Eduard - Gabriel Munteanu --- hw/pci.c | 7 +++++++ hw/pci.h | 9 +++++++++ hw/pci_internals.h | 1 + 3 files changed, 17 insertions(+), 0 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 0875654..7c8762c 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -745,6 +745,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, return NULL; } pci_dev->bus = bus; + pci_dev->dma.mmu = &bus->mmu; pci_dev->devfn = devfn; pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); pci_dev->irq_state = 0; @@ -2161,3 +2162,9 @@ int pci_qdev_find_device(const char *id, PCIDevice **pdev) return rc; } + +void pci_register_iommu(PCIDevice *dev, DMATranslateFunc *translate) +{ + dev->bus->mmu.iommu = &dev->qdev; + dev->bus->mmu.translate = translate; +} diff --git a/hw/pci.h b/hw/pci.h index c6a6eb6..f3b51ec 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -5,6 +5,7 @@ #include "qobject.h" #include "qdev.h" +#include "dma_rw.h" /* PCI includes legacy ISA access. */ #include "isa.h" @@ -129,6 +130,10 @@ enum { struct PCIDevice { DeviceState qdev; + + /* For devices which do DMA. */ + DMADevice dma; + /* PCI config space */ uint8_t *config; @@ -271,6 +276,8 @@ void pci_bridge_update_mappings(PCIBus *b); void pci_device_deassert_intx(PCIDevice *dev); +void pci_register_iommu(PCIDevice *dev, DMATranslateFunc *translate); + static inline void pci_set_byte(uint8_t *config, uint8_t val) { @@ -475,4 +482,6 @@ static inline uint32_t pci_config_size(const PCIDevice *d) return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; } +DEFINE_DMA_OPS(pci, PCIDevice, dma) + #endif diff --git a/hw/pci_internals.h b/hw/pci_internals.h index fbe1866..6452e8c 100644 --- a/hw/pci_internals.h +++ b/hw/pci_internals.h @@ -16,6 +16,7 @@ extern struct BusInfo pci_bus_info; struct PCIBus { BusState qbus; + DMAMmu mmu; uint8_t devfn_min; pci_set_irq_fn set_irq; pci_map_irq_fn map_irq; -- 1.7.3.4