qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Eduardo Habkost <ehabkost@redhat.com>
To: Anthony Liguori <anthony@codemonkey.ws>
Cc: qemu-devel@nongnu.org
Subject: [Qemu-devel] [RHEL6 qemu-kvm PATCH 06/11] cpu defs: remove replicated flags from Intel
Date: Thu,  2 Jun 2011 16:13:05 -0300	[thread overview]
Message-ID: <1307041990-26194-7-git-send-email-ehabkost@redhat.com> (raw)
In-Reply-To: <1307041990-26194-1-git-send-email-ehabkost@redhat.com>

This patch removes the replicated feature flags from cpuid 8000_0001:edx
(extfeature_edx) from Intel models, as the duplicated feature flags are present
only on AMD CPUs. On Intel models, only the i64, syscall, and xd flags are kept
on extfeature_edx.

This is based on a previous patch from John Cooper where this was introduced
with many other changes at the same time. Original John's patch submission is
at Message-ID: <4DDAD5E7.2020002@redhat.com>, <http://marc.info/?l=qemu-devel&m=130618871926030>.

Original John's patch description was:

    cpu model bug fixes and definition corrections

    This patch was intended to address the replicated feature
    flags in cpuid 8000_0001:edx from cpuid 0000_0001:edx.
    This is due to AMD's definition where these flags are
    mostly cloned in the 8000_0001:edx cpuid function.
    qemu64 attempted to glue together the respective Intel
    and AMD nearly disjoint features and this propagated to
    the new Intel models as doing so was believed conservative
    at the time.  However after further soak and test lugging
    around this cruft doesn't provide any value, could
    conceivably confuse a guest, and has confused users trying
    to maintain/add cpu definitions.  This also caused issues
    for libvirt attempting to track this mis-encoding.

    So we've here tossed out the AMD replicated definitions
    from the Intel models, added a few replications into AMD
    definitions which were missing according to AMD's latest
    CPUID document, and reordered the config file flags to
    follow intuitive sequential bit ordering.  Also two flag
    name aliases were added for clarity to Intel models.  The
    end result being the models definitions now conform to
    their respective cpuid specifications sans x2apic which is
    emulated by kvm.

    This was tested with the following combinations:

        [Conroe, Penryn, Nehalem] x [F12-64, win64, win32] -- Intel host
        [Opteron_G1, Opteron_G2, Opteron_G3] x [F12-64, win64, win32] -- AMD host

    Yielding successful boots in all cases.

    Signed-off-by: john cooper <john.cooper@redhat.com>

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 sysconfigs/target/target-x86_64.conf |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf
index fd4e421..09b30a4 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -9,7 +9,7 @@
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
    feature_ecx = "sse3 ssse3 x2apic"
-   extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu    i64 syscall xd"
+   extfeature_edx = "i64 syscall xd"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)"
@@ -23,7 +23,7 @@
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
    feature_ecx = "sse3 cx16 ssse3 sse4.1 x2apic"
-   extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu    i64 syscall xd"
+   extfeature_edx = "i64 syscall xd"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)"
@@ -37,7 +37,7 @@
    stepping = "3"
    feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc pse de fpu    mtrr clflush mca pse36"
    feature_ecx = "sse3 cx16 ssse3 sse4.1 sse4.2 popcnt x2apic"
-   extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu    i64 syscall xd"
+   extfeature_edx = "i64 syscall xd"
    extfeature_ecx = "lahf_lm"
    xlevel = "0x8000000A"
    model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
-- 
1.7.3.2

  parent reply	other threads:[~2011-06-02 19:13 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-06-02 19:12 [Qemu-devel] [RHEL6 qemu-kvm PATCH 00/11] cpu model bug fixes and definition corrections (v2) Eduardo Habkost
2011-06-02 19:13 ` [Qemu-devel] [RHEL6 qemu-kvm PATCH 01/11] correct archaic CPU model "model" field for Intel CPUs Eduardo Habkost
2011-06-02 19:13 ` [Qemu-devel] [RHEL6 qemu-kvm PATCH 02/11] Allow an optional qemu_early_init_vcpu() Eduardo Habkost
2011-06-02 19:13 ` [Qemu-devel] [RHEL6 qemu-kvm PATCH 03/11] Add kvm emulated x2apic flag to config defined cpu models (v2) Eduardo Habkost
2011-06-02 19:13 ` [Qemu-devel] [RHEL6 qemu-kvm PATCH 04/11] Support -readconfig "?" to debug config file loading Eduardo Habkost
2011-06-02 19:13 ` [Qemu-devel] [RHEL6 qemu-kvm PATCH 05/11] cpu defs: use Intel flag names for Intel models Eduardo Habkost
2011-06-02 19:13 ` Eduardo Habkost [this message]
2011-06-02 19:13 ` [Qemu-devel] [RHEL6 qemu-kvm PATCH 07/11] cpu defs: uncomment empty extfeatures_ecx definition for Opteron_G1 Eduardo Habkost
2011-06-02 19:13 ` [Qemu-devel] [RHEL6 qemu-kvm PATCH 08/11] reorder cpuid feature bits on target-x86_64.conf Eduardo Habkost
2011-06-02 19:13 ` [Qemu-devel] [RHEL6 qemu-kvm PATCH 09/11] cpu defs: add pse36, mca, mtrr to AMD CPU definitions Eduardo Habkost
2011-06-02 19:13 ` [Qemu-devel] [RHEL6 qemu-kvm PATCH 10/11] add Westmere as a qemu cpu model Eduardo Habkost
2011-06-02 19:13 ` [Qemu-devel] [RHEL6 qemu-kvm PATCH 11/11] add "default" pseudo CPU model name Eduardo Habkost
2011-06-02 19:34 ` [Qemu-devel] [PATCH 00/11] cpu model bug fixes and definition corrections (v2) Eduardo Habkost
2011-06-02 22:51   ` Jan Kiszka
2011-06-03 14:38     ` Eduardo Habkost
2011-06-03 14:51       ` Jan Kiszka
2011-06-09  6:43         ` Markus Armbruster

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1307041990-26194-7-git-send-email-ehabkost@redhat.com \
    --to=ehabkost@redhat.com \
    --cc=anthony@codemonkey.ws \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).