From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:58243) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QTcY9-0002C2-9g for qemu-devel@nongnu.org; Mon, 06 Jun 2011 12:21:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QTcY6-0002l2-6z for qemu-devel@nongnu.org; Mon, 06 Jun 2011 12:21:08 -0400 Received: from fmmailgate02.web.de ([217.72.192.227]:33086) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QTcY5-0002jc-HZ for qemu-devel@nongnu.org; Mon, 06 Jun 2011 12:21:05 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 6 Jun 2011 18:20:52 +0200 Message-Id: <1307377259-41434-4-git-send-email-andreas.faerber@web.de> In-Reply-To: <1307377259-41434-3-git-send-email-andreas.faerber@web.de> References: <1307377259-41434-1-git-send-email-andreas.faerber@web.de> <1307377259-41434-2-git-send-email-andreas.faerber@web.de> <1307377259-41434-3-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: andreas.faerber@web.de Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC 03/10] parallel: Allow to reconfigure ISA I/O base List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , hpoussin@reactos.org, kraxel@redhat.com Signed-off-by: Andreas F=C3=A4rber --- hw/isa.h | 3 ++ hw/parallel.c | 70 +++++++++++++++++++++++++++++++++++++++------------= ------ 2 files changed, 51 insertions(+), 22 deletions(-) diff --git a/hw/isa.h b/hw/isa.h index 789d91c..2bd8c82 100644 --- a/hw/isa.h +++ b/hw/isa.h @@ -41,6 +41,9 @@ extern target_phys_addr_t isa_mem_base; =20 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size); =20 +/* parallel.c */ +void parallel_isa_reconfigure_iobase(ISADevice *dev, uint32_t base); + /* dma.c */ int DMA_get_channel_mode (int nchan); int DMA_read_memory (int nchan, void *buf, int pos, int size); diff --git a/hw/parallel.c b/hw/parallel.c index cc853a5..5cb3856 100644 --- a/hw/parallel.c +++ b/hw/parallel.c @@ -446,6 +446,53 @@ static void parallel_reset(void *opaque) s->last_read_offset =3D ~0U; } =20 +static void parallel_isa_init_iobase(ISAParallelState *isa) +{ + ISADevice *dev =3D &isa->dev; + ParallelState *s =3D &isa->state; + int base; + + base =3D isa->iobase; + if (s->hw_driver) { + register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s); + register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s); + isa_init_ioport_range(dev, base, 8); + + register_ioport_write(base + 4, 1, 2, parallel_ioport_eppdata_wr= ite_hw2, s); + register_ioport_read(base + 4, 1, 2, parallel_ioport_eppdata_rea= d_hw2, s); + register_ioport_write(base + 4, 1, 4, parallel_ioport_eppdata_wr= ite_hw4, s); + register_ioport_read(base + 4, 1, 4, parallel_ioport_eppdata_rea= d_hw4, s); + isa_init_ioport(dev, base + 4); + register_ioport_write(base + 0x400, 8, 1, parallel_ioport_ecp_wr= ite, s); + register_ioport_read(base + 0x400, 8, 1, parallel_ioport_ecp_rea= d, s); + isa_init_ioport_range(dev, base + 0x400, 8); + } else { + register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s); + register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s); + isa_init_ioport_range(dev, base, 8); + } +} + +void parallel_isa_reconfigure_iobase(ISADevice *dev, uint32_t base) +{ + ISAParallelState *isa =3D DO_UPCAST(ISAParallelState, dev, dev); + ParallelState *s =3D &isa->state; + + if (base !=3D isa->iobase) { + isa_discard_ioport_range(dev, base, 8); + isa_unassign_ioport(base, 8); + if (s->hw_driver) { + isa_discard_ioport_range(dev, base + 4, 1); + isa_unassign_ioport(base + 4, 1); + isa_discard_ioport_range(dev, base + 0x400, 8); + isa_unassign_ioport(base + 0x400, 8); + } + + isa->iobase =3D base; + parallel_isa_init_iobase(isa); + } +} + static const int isa_parallel_io[MAX_PARALLEL_PORTS] =3D { 0x378, 0x278,= 0x3bc }; =20 static int parallel_isa_initfn(ISADevice *dev) @@ -453,7 +500,6 @@ static int parallel_isa_initfn(ISADevice *dev) static int index; ISAParallelState *isa =3D DO_UPCAST(ISAParallelState, dev, dev); ParallelState *s =3D &isa->state; - int base; uint8_t dummy; =20 if (!s->chr) { @@ -469,7 +515,6 @@ static int parallel_isa_initfn(ISADevice *dev) isa->iobase =3D isa_parallel_io[isa->index]; index++; =20 - base =3D isa->iobase; isa_init_irq(dev, &s->irq, isa->isairq); qemu_register_reset(parallel_reset, s); =20 @@ -477,26 +522,7 @@ static int parallel_isa_initfn(ISADevice *dev) s->hw_driver =3D 1; s->status =3D dummy; } - - if (s->hw_driver) { - register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s); - register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s); - isa_init_ioport_range(dev, base, 8); - - register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_writ= e_hw2, s); - register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_= hw2, s); - register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_writ= e_hw4, s); - register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_= hw4, s); - isa_init_ioport(dev, base+4); - register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_writ= e, s); - register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read,= s); - isa_init_ioport_range(dev, base+0x400, 8); - } - else { - register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s); - register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s); - isa_init_ioport_range(dev, base, 8); - } + parallel_isa_init_iobase(isa); return 0; } =20 --=20 1.7.5.3