From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34121) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUE4e-00086e-Ln for qemu-devel@nongnu.org; Wed, 08 Jun 2011 04:25:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QUE4c-0007iX-Pz for qemu-devel@nongnu.org; Wed, 08 Jun 2011 04:25:12 -0400 Received: from mtagate3.uk.ibm.com ([194.196.100.163]:56856) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUE4b-0007hr-NU for qemu-devel@nongnu.org; Wed, 08 Jun 2011 04:25:10 -0400 Received: from d06nrmr1806.portsmouth.uk.ibm.com (d06nrmr1806.portsmouth.uk.ibm.com [9.149.39.193]) by mtagate3.uk.ibm.com (8.13.1/8.13.1) with ESMTP id p588P5H7025141 for ; Wed, 8 Jun 2011 08:25:05 GMT Received: from d06av07.portsmouth.uk.ibm.com (d06av07.portsmouth.uk.ibm.com [9.149.37.248]) by d06nrmr1806.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p588P2sI2666702 for ; Wed, 8 Jun 2011 09:25:05 +0100 Received: from d06av07.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p588P2CJ013826 for ; Wed, 8 Jun 2011 02:25:02 -0600 From: Stefan Hajnoczi Date: Wed, 8 Jun 2011 09:24:46 +0100 Message-Id: <1307521488-6066-5-git-send-email-stefanha@linux.vnet.ibm.com> In-Reply-To: <1307521488-6066-1-git-send-email-stefanha@linux.vnet.ibm.com> References: <1307521488-6066-1-git-send-email-stefanha@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 4/6] m68k: Replace gen_im32() by tcg_const_i32() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Laurent Vivier , Stefan Hajnoczi From: Laurent Vivier Signed-off-by: Laurent Vivier Reviewed-by: Andreas F=C3=A4rber Signed-off-by: Stefan Hajnoczi --- target-m68k/translate.c | 43 ++++++++++++++++++++---------------------= -- 1 files changed, 20 insertions(+), 23 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 9e5578d..26f0ee4 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -171,9 +171,6 @@ typedef void (*disas_proc)(DisasContext *, uint16_t); static void disas_##name (DisasContext *s, uint16_t insn) #endif =20 -/* FIXME: Remove this. */ -#define gen_im32(val) tcg_const_i32(val) - /* Generate a load from the specified address. Narrow values are sign extended to full register width. */ static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int= sign) @@ -339,7 +336,7 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsi= ze, TCGv base) if ((ext & 0x80) =3D=3D 0) { /* base not suppressed */ if (IS_NULL_QREG(base)) { - base =3D gen_im32(offset + bd); + base =3D tcg_const_i32(offset + bd); bd =3D 0; } if (!IS_NULL_QREG(add)) { @@ -355,7 +352,7 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsi= ze, TCGv base) add =3D tmp; } } else { - add =3D gen_im32(bd); + add =3D tcg_const_i32(bd); } if ((ext & 3) !=3D 0) { /* memory indirect */ @@ -536,15 +533,15 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn,= int opsize) case 0: /* Absolute short. */ offset =3D ldsw_code(s->pc); s->pc +=3D 2; - return gen_im32(offset); + return tcg_const_i32(offset); case 1: /* Absolute long. */ offset =3D read_im32(s); - return gen_im32(offset); + return tcg_const_i32(offset); case 2: /* pc displacement */ offset =3D s->pc; offset +=3D ldsw_code(s->pc); s->pc +=3D 2; - return gen_im32(offset); + return tcg_const_i32(offset); case 3: /* pc index+displacement. */ return gen_lea_indexed(s, opsize, NULL_QREG); case 4: /* Immediate. */ @@ -1209,16 +1206,16 @@ DISAS_INSN(arith_im) break; case 2: /* subi */ tcg_gen_mov_i32(dest, src1); - gen_helper_xflag_lt(QREG_CC_X, dest, gen_im32(im)); + gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); tcg_gen_subi_i32(dest, dest, im); - gen_update_cc_add(dest, gen_im32(im)); + gen_update_cc_add(dest, tcg_const_i32(im)); s->cc_op =3D CC_OP_SUB; break; case 3: /* addi */ tcg_gen_mov_i32(dest, src1); tcg_gen_addi_i32(dest, dest, im); - gen_update_cc_add(dest, gen_im32(im)); - gen_helper_xflag_lt(QREG_CC_X, dest, gen_im32(im)); + gen_update_cc_add(dest, tcg_const_i32(im)); + gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); s->cc_op =3D CC_OP_ADD; break; case 5: /* eori */ @@ -1228,7 +1225,7 @@ DISAS_INSN(arith_im) case 6: /* cmpi */ tcg_gen_mov_i32(dest, src1); tcg_gen_subi_i32(dest, dest, im); - gen_update_cc_add(dest, gen_im32(im)); + gen_update_cc_add(dest, tcg_const_i32(im)); s->cc_op =3D CC_OP_SUB; break; default: @@ -1324,8 +1321,8 @@ DISAS_INSN(clr) default: abort(); } - DEST_EA(insn, opsize, gen_im32(0), NULL); - gen_logic_cc(s, gen_im32(0)); + DEST_EA(insn, opsize, tcg_const_i32(0), NULL); + gen_logic_cc(s, tcg_const_i32(0)); } =20 static TCGv gen_get_ccr(DisasContext *s) @@ -1589,7 +1586,7 @@ DISAS_INSN(jump) } if ((insn & 0x40) =3D=3D 0) { /* jsr */ - gen_push(s, gen_im32(s->pc)); + gen_push(s, tcg_const_i32(s->pc)); } gen_jmp(s, tmp); } @@ -1617,7 +1614,7 @@ DISAS_INSN(addsubq) tcg_gen_addi_i32(dest, dest, val); } } else { - src2 =3D gen_im32(val); + src2 =3D tcg_const_i32(val); if (insn & 0x0100) { gen_helper_xflag_lt(QREG_CC_X, dest, src2); tcg_gen_subi_i32(dest, dest, val); @@ -1666,7 +1663,7 @@ DISAS_INSN(branch) } if (op =3D=3D 1) { /* bsr */ - gen_push(s, gen_im32(s->pc)); + gen_push(s, tcg_const_i32(s->pc)); } gen_flush_cc_op(s); if (op > 1) { @@ -1757,7 +1754,7 @@ DISAS_INSN(mov3q) val =3D (insn >> 9) & 7; if (val =3D=3D 0) val =3D -1; - src =3D gen_im32(val); + src =3D tcg_const_i32(val); gen_logic_cc(s, src); DEST_EA(insn, OS_LONG, src, NULL); } @@ -1883,7 +1880,7 @@ DISAS_INSN(shift_im) tmp =3D (insn >> 9) & 7; if (tmp =3D=3D 0) tmp =3D 8; - shift =3D gen_im32(tmp); + shift =3D tcg_const_i32(tmp); /* No need to flush flags becuse we know we will set C flag. */ if (insn & 0x100) { gen_helper_shl_cc(reg, cpu_env, reg, shift); @@ -2191,7 +2188,7 @@ DISAS_INSN(fpu) switch ((ext >> 10) & 7) { case 4: /* FPCR */ /* Not implemented. Always return zero. */ - tmp32 =3D gen_im32(0); + tmp32 =3D tcg_const_i32(0); break; case 1: /* FPIAR */ case 2: /* FPSR */ @@ -2592,7 +2589,7 @@ DISAS_INSN(mac) /* Skip the accumulate if the value is already saturated. */ l1 =3D gen_new_label(); tmp =3D tcg_temp_new(); - gen_op_and32(tmp, QREG_MACSR, gen_im32(MACSR_PAV0 << acc)); + gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); gen_op_jmp_nz32(tmp, l1); } #endif @@ -2626,7 +2623,7 @@ DISAS_INSN(mac) /* Skip the accumulate if the value is already saturated. *= / l1 =3D gen_new_label(); tmp =3D tcg_temp_new(); - gen_op_and32(tmp, QREG_MACSR, gen_im32(MACSR_PAV0 << acc)); + gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << ac= c)); gen_op_jmp_nz32(tmp, l1); } #endif --=20 1.7.4.4