From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34151) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUE4i-00087z-N5 for qemu-devel@nongnu.org; Wed, 08 Jun 2011 04:25:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QUE4f-0007jZ-VV for qemu-devel@nongnu.org; Wed, 08 Jun 2011 04:25:16 -0400 Received: from mtagate1.uk.ibm.com ([194.196.100.161]:51414) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUE4e-0007ip-L3 for qemu-devel@nongnu.org; Wed, 08 Jun 2011 04:25:13 -0400 Received: from d06nrmr1507.portsmouth.uk.ibm.com (d06nrmr1507.portsmouth.uk.ibm.com [9.149.38.233]) by mtagate1.uk.ibm.com (8.13.1/8.13.1) with ESMTP id p588P5nH003959 for ; Wed, 8 Jun 2011 08:25:05 GMT Received: from d06av07.portsmouth.uk.ibm.com (d06av07.portsmouth.uk.ibm.com [9.149.37.248]) by d06nrmr1507.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p588P4cn1519758 for ; Wed, 8 Jun 2011 09:25:04 +0100 Received: from d06av07.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av07.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p588P22M013842 for ; Wed, 8 Jun 2011 02:25:03 -0600 From: Stefan Hajnoczi Date: Wed, 8 Jun 2011 09:24:47 +0100 Message-Id: <1307521488-6066-6-git-send-email-stefanha@linux.vnet.ibm.com> In-Reply-To: <1307521488-6066-1-git-send-email-stefanha@linux.vnet.ibm.com> References: <1307521488-6066-1-git-send-email-stefanha@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 5/6] target-i386: Make x86 mfence and lfence illegal without SSE2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Martin Simmons , Stefan Hajnoczi From: Martin Simmons While trying to use qemu -cpu pentium3 to test for incorrect uses of certain SSE2 instructions, I found that QEMU allowed the mfence and lfence instructions to be executed even though Pentium 3 doesn't support them. According to the processor specs (and experience on a real Pentium 3), these instructions are only available with SSE2, but QEMU is checking for SSE. The check for the related sfence instruction is correct (it works with SSE). This trival patch fixes the test. Signed-off-by: Martin Simmons Signed-off-by: Stefan Hajnoczi --- target-i386/translate.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 199302e..10bd72a 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7538,7 +7538,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) break; case 5: /* lfence */ case 6: /* mfence */ - if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE)) + if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2)) goto illegal_op; break; case 7: /* sfence / clflush */ -- 1.7.4.4