From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:42445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QWJVy-0006rz-SF for qemu-devel@nongnu.org; Mon, 13 Jun 2011 22:38:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QWJVx-0006fy-7T for qemu-devel@nongnu.org; Mon, 13 Jun 2011 22:38:02 -0400 Received: from fmmailgate02.web.de ([217.72.192.227]:57738) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QWJVw-0006fl-Kl for qemu-devel@nongnu.org; Mon, 13 Jun 2011 22:38:00 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 14 Jun 2011 04:37:35 +0200 Message-Id: <1308019077-61957-2-git-send-email-andreas.faerber@web.de> In-Reply-To: <1308019077-61957-1-git-send-email-andreas.faerber@web.de> References: <1308019077-61957-1-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: andreas.faerber@web.de Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH RFC 01/23] prep: Refactor CPU initialization List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= To cope with upcoming PReP machines and as a first step towards pending qdev'ification of the ppc CPU, move CPU initialization to a helper function, similar to pc_new_cpu(). Cc: Herv=C3=A9 Poussineau Signed-off-by: Andreas F=C3=A4rber --- hw/ppc_prep.c | 47 +++++++++++++++++++++++++++++++---------------- 1 files changed, 31 insertions(+), 16 deletions(-) diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 0e9cfc2..b3efd3c 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -525,6 +525,36 @@ static void cpu_request_exit(void *opaque, int irq, = int level) } } =20 +static void prep_cpu_reset(void *opaque) +{ + CPUState *env =3D opaque; + + cpu_reset(env); +} + +static CPUState *ppc_prep_new_cpu(const char *cpu_model) +{ + CPUState *env; + + env =3D cpu_init(cpu_model); + if (!env) { + fprintf(stderr, "Unable to find PowerPC CPU definition\n"); + exit(1); + } + if (PPC_INPUT(env) !=3D PPC_FLAGS_INPUT_6xx) { + hw_error("Only 6xx bus is supported on PREP machine\n"); + } + if (env->flags & POWERPC_FLAG_RTC_CLK) { + /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ + cpu_ppc_tb_init(env, 7812500UL); + } else { + /* Set time-base frequency to 100 Mhz */ + cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); + } + qemu_register_reset(prep_cpu_reset, env); + return env; +} + /* PowerPC PREP hardware initialisation */ static void ppc_prep_init (ram_addr_t ram_size, const char *boot_device, @@ -557,19 +587,7 @@ static void ppc_prep_init (ram_addr_t ram_size, if (cpu_model =3D=3D NULL) cpu_model =3D "602"; for (i =3D 0; i < smp_cpus; i++) { - env =3D cpu_init(cpu_model); - if (!env) { - fprintf(stderr, "Unable to find PowerPC CPU definition\n"); - exit(1); - } - if (env->flags & POWERPC_FLAG_RTC_CLK) { - /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ - cpu_ppc_tb_init(env, 7812500UL); - } else { - /* Set time-base frequency to 100 Mhz */ - cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); - } - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); + env =3D ppc_prep_new_cpu(cpu_model); } =20 /* allocate RAM */ @@ -644,9 +662,6 @@ static void ppc_prep_init (ram_addr_t ram_size, } =20 isa_mem_base =3D 0xc0000000; - if (PPC_INPUT(env) !=3D PPC_FLAGS_INPUT_6xx) { - hw_error("Only 6xx bus is supported on PREP machine\n"); - } i8259 =3D i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); pci_bus =3D pci_prep_init(i8259); /* Hmm, prep has no pci-isa bridge ??? */ --=20 1.7.5.3