From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:57261) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QWJW5-0006tZ-5P for qemu-devel@nongnu.org; Mon, 13 Jun 2011 22:38:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QWJVx-0006g7-MD for qemu-devel@nongnu.org; Mon, 13 Jun 2011 22:38:08 -0400 Received: from fmmailgate02.web.de ([217.72.192.227]:57739) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QWJVw-0006fo-VG for qemu-devel@nongnu.org; Mon, 13 Jun 2011 22:38:01 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 14 Jun 2011 04:37:36 +0200 Message-Id: <1308019077-61957-3-git-send-email-andreas.faerber@web.de> In-Reply-To: <1308019077-61957-2-git-send-email-andreas.faerber@web.de> References: <1308019077-61957-1-git-send-email-andreas.faerber@web.de> <1308019077-61957-2-git-send-email-andreas.faerber@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: andreas.faerber@web.de Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC 02/23] prep: qdev'ify PCI List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Alexander Graf , "Michael S. Tsirkin" Don't always keep pointer to PIC, but keep only references to required IRQs. Add a PCI host. Signed-off-by: Herv=C3=A9 Poussineau Avoid adding qemu_irq state by reusing SysBus facilities. This allows to qdev'ify the PCIDevice, too, by banning hardcoded IRQ numbers into pci_prep_init() wrapper. Cc: Michael S. Tsirkin Cc: Alexander Graf Signed-off-by: Andreas F=C3=A4rber --- hw/prep_pci.c | 126 ++++++++++++++++++++++++++++++++++++++++++++-------= ------ 1 files changed, 97 insertions(+), 29 deletions(-) diff --git a/hw/prep_pci.c b/hw/prep_pci.c index f88b825..2554d86 100644 --- a/hw/prep_pci.c +++ b/hw/prep_pci.c @@ -2,6 +2,8 @@ * QEMU PREP PCI host * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2010 Herve Poussineau + * Copyright (c) 2010-2011 Andreas Faerber * * Permission is hereby granted, free of charge, to any person obtaining= a copy * of this software and associated documentation files (the "Software"),= to deal @@ -27,7 +29,14 @@ #include "pci_host.h" #include "prep_pci.h" =20 -typedef PCIHostState PREPPCIState; +typedef struct PREPPCIState { + PCIHostState host_state; +} PREPPCIState; + +typedef struct PRePPCIBusState { + SysBusDevice busdev; + PREPPCIState state; +} PRePPCIBusState; =20 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr) { @@ -43,28 +52,28 @@ static inline uint32_t PPC_PCIIO_config(target_phys_a= ddr_t addr) static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uin= t32_t val) { PREPPCIState *s =3D opaque; - pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1); + pci_data_write(s->host_state.bus, PPC_PCIIO_config(addr), val, 1); } =20 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uin= t32_t val) { PREPPCIState *s =3D opaque; val =3D bswap16(val); - pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2); + pci_data_write(s->host_state.bus, PPC_PCIIO_config(addr), val, 2); } =20 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uin= t32_t val) { PREPPCIState *s =3D opaque; val =3D bswap32(val); - pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4); + pci_data_write(s->host_state.bus, PPC_PCIIO_config(addr), val, 4); } =20 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) { PREPPCIState *s =3D opaque; uint32_t val; - val =3D pci_data_read(s->bus, PPC_PCIIO_config(addr), 1); + val =3D pci_data_read(s->host_state.bus, PPC_PCIIO_config(addr), 1); return val; } =20 @@ -72,7 +81,7 @@ static uint32_t PPC_PCIIO_readw (void *opaque, target_p= hys_addr_t addr) { PREPPCIState *s =3D opaque; uint32_t val; - val =3D pci_data_read(s->bus, PPC_PCIIO_config(addr), 2); + val =3D pci_data_read(s->host_state.bus, PPC_PCIIO_config(addr), 2); val =3D bswap16(val); return val; } @@ -81,7 +90,7 @@ static uint32_t PPC_PCIIO_readl (void *opaque, target_p= hys_addr_t addr) { PREPPCIState *s =3D opaque; uint32_t val; - val =3D pci_data_read(s->bus, PPC_PCIIO_config(addr), 4); + val =3D pci_data_read(s->host_state.bus, PPC_PCIIO_config(addr), 4); val =3D bswap32(val); return val; } @@ -105,40 +114,99 @@ static int prep_map_irq(PCIDevice *pci_dev, int irq= _num) =20 static void prep_set_irq(void *opaque, int irq_num, int level) { - qemu_irq *pic =3D opaque; + PRePPCIBusState *s =3D opaque; + SysBusDevice *sysbus =3D &s->busdev; =20 - qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level); + if (sysbus->irqp[irq_num] !=3D NULL) { + qemu_set_irq(*sysbus->irqp[irq_num], level); + } } =20 +static int prep_pci_host_init(PCIDevice *d) +{ + pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA); + pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN); + d->config[0x08] =3D 0x00; // revision + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); + d->config[0x0C] =3D 0x08; // cache_line_size + d->config[0x0D] =3D 0x10; // latency_timer + d->config[0x34] =3D 0x00; // capabilities_pointer + + return 0; +} + +/* Motorola Raven */ +static PCIDeviceInfo prep_pci_host_info =3D { + .qdev.name =3D "prep-pci", + .qdev.size =3D sizeof(PCIDevice), + .init =3D prep_pci_host_init, + .qdev.props =3D (Property[]) { + DEFINE_PROP_END_OF_LIST() + }, +}; + PCIBus *pci_prep_init(qemu_irq *pic) { - PREPPCIState *s; - PCIDevice *d; - int PPC_io_memory; + DeviceState *dev; + SysBusDevice *sysbus; + + /* PReP PCI bus */ + dev =3D qdev_create(NULL, "prep-pci"); + sysbus =3D sysbus_from_qdev(dev); =20 - s =3D qemu_mallocz(sizeof(PREPPCIState)); - s->bus =3D pci_register_bus(NULL, "pci", - prep_set_irq, prep_map_irq, pic, 0, 4); + /* Allocate and initialize both IRQs before init */ + sysbus_init_irq(sysbus, &pic[9]); + sysbus_init_irq(sysbus, &pic[11]); =20 - pci_host_conf_register_ioport(0xcf8, s); + qdev_init_nofail(dev); =20 - pci_host_data_register_ioport(0xcfc, s); + sysbus_mmio_map(sysbus, 0, 0x80800000); + + return (PCIBus *)qdev_get_child_bus(dev, "pci"); +} + +static int prep_pci_sysbus_init(SysBusDevice *dev) +{ + PRePPCIBusState *sysbus =3D FROM_SYSBUS(PRePPCIBusState, dev); + PREPPCIState *s =3D &sysbus->state; + PCIDevice *d; + int PPC_io_memory; + + /* Allocate two IRQs if necessary and NULL-initialize */ + while (sysbus->busdev.num_irq < 2) { + sysbus_init_irq(&sysbus->busdev, NULL); + } =20 PPC_io_memory =3D cpu_register_io_memory(PPC_PCIIO_read, PPC_PCIIO_write, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); + sysbus_init_mmio(dev, 0x00400000, PPC_io_memory); =20 - /* PCI host bridge */ - d =3D pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven= ", - sizeof(PCIDevice), 0, NULL, NULL); - pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA); - pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN); - d->config[0x08] =3D 0x00; // revision - pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); - d->config[0x0C] =3D 0x08; // cache_line_size - d->config[0x0D] =3D 0x10; // latency_timer - d->config[0x34] =3D 0x00; // capabilities_pointer + s->host_state.bus =3D pci_register_bus(&sysbus->busdev.qdev, "pci", + prep_set_irq, + prep_map_irq, sysbus, 0, 2); + + pci_host_conf_register_ioport(0xcf8, &s->host_state); + pci_host_data_register_ioport(0xcfc, &s->host_state); + + d =3D pci_create_simple(s->host_state.bus, 0, "prep-pci"); + + return 0; +} + +static SysBusDeviceInfo prep_pci_sysbus_info =3D { + .qdev.name =3D "prep-pci", + .qdev.size =3D sizeof(PRePPCIBusState), + .init =3D prep_pci_sysbus_init, + .qdev.props =3D (Property[]) { + DEFINE_PROP_END_OF_LIST() + }, +}; =20 - return s->bus; +static void prep_pci_register_devices(void) +{ + sysbus_register_withprop(&prep_pci_sysbus_info); + pci_qdev_register(&prep_pci_host_info); } + +device_init(prep_pci_register_devices) --=20 1.7.5.3