From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:36289) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QZRJ8-00005m-P2 for qemu-devel@nongnu.org; Wed, 22 Jun 2011 13:33:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QZRJ4-0000hr-Gw for qemu-devel@nongnu.org; Wed, 22 Jun 2011 13:33:42 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:54088) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QZRJ4-0000hV-4b for qemu-devel@nongnu.org; Wed, 22 Jun 2011 13:33:38 -0400 From: Peter Maydell Date: Wed, 22 Jun 2011 18:33:33 +0100 Message-Id: <1308764013-18149-9-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1308764013-18149-1-git-send-email-peter.maydell@linaro.org> References: <1308764013-18149-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 8/8] target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK access List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori , qemu-devel@nongnu.org Cc: Aurelien Jarno From: Sebastian Huber Correct the decode of the register numbers for BASEPRI, BASEPRI_MAX and FAULTMASK, according to "ARMv7-M Architecture Reference Manual" issue D section "B5.2.3 MRS" and "B5.2.3 MSR". Signed-off-by: Sebastian Huber Signed-off-by: Peter Maydell --- target-arm/helper.c | 24 ++++++++++++------------ 1 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 9785cc5..a0f2314 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2128,11 +2128,11 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp; case 16: /* PRIMASK */ return (env->uncached_cpsr & CPSR_I) != 0; - case 17: /* FAULTMASK */ - return (env->uncached_cpsr & CPSR_F) != 0; - case 18: /* BASEPRI */ - case 19: /* BASEPRI_MAX */ + case 17: /* BASEPRI */ + case 18: /* BASEPRI_MAX */ return env->v7m.basepri; + case 19: /* FAULTMASK */ + return (env->uncached_cpsr & CPSR_F) != 0; case 20: /* CONTROL */ return env->v7m.control; default: @@ -2184,20 +2184,20 @@ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val) else env->uncached_cpsr &= ~CPSR_I; break; - case 17: /* FAULTMASK */ - if (val & 1) - env->uncached_cpsr |= CPSR_F; - else - env->uncached_cpsr &= ~CPSR_F; - break; - case 18: /* BASEPRI */ + case 17: /* BASEPRI */ env->v7m.basepri = val & 0xff; break; - case 19: /* BASEPRI_MAX */ + case 18: /* BASEPRI_MAX */ val &= 0xff; if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) env->v7m.basepri = val; break; + case 19: /* FAULTMASK */ + if (val & 1) + env->uncached_cpsr |= CPSR_F; + else + env->uncached_cpsr &= ~CPSR_F; + break; case 20: /* CONTROL */ env->v7m.control = val & 3; switch_v7m_sp(env, (val & 2) != 0); -- 1.7.1