[Qemu-devel] [PATCH v2 0/8] SPARC64: Implement sparcv9 ldfa/stfa instructions

[Qemu-devel] [PATCH v2 0/8] SPARC64: Implement sparcv9 ldfa/stfa instructions

[Tsuneo Saito]

This patch series implements sparcv9 stfa/ldfa instructions that
implementations seem to be left unfinished.
This patch also adds fp_disabled exception checks on stfa/ldfa
as they are FP instructions.

v2:
 * checked by checkpatch.pl.
 * added UA2007 block-transfer ASIs.
 * added JPS1 little-endian block-transfer ASIs that seem forgotten.

 target-sparc/op_helper.c |   75 ++++++++++++++++++++++++++++++---------------
 target-sparc/translate.c |   20 +++++++++++-
 2 files changed, 68 insertions(+), 27 deletions(-)

-- 
1.7.5.4

[Qemu-devel] [PATCH v2 1/8] SPARC64: Implement ldfa/lddfa/ldqfa instructions properly

[Tsuneo Saito]

This patch implements sparcv9 ldfa/lddfa/ldqfa instructions
with non block-load ASIs.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/op_helper.c |   16 +++++++++++-----
 1 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index fd0cfbd..a75ac4f 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -3331,7 +3331,7 @@ void helper_ldda_asi(target_ulong addr, int asi, int rd)
 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
 {
     unsigned int i;
-    target_ulong val;
+    CPU_DoubleU u;
 
     helper_check_align(addr, 3);
     addr = asi_address_mask(env, asi, addr);
@@ -3371,17 +3371,23 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
         break;
     }
 
-    val = helper_ld_asi(addr, asi, size, 0);
     switch(size) {
     default:
     case 4:
-        *((uint32_t *)&env->fpr[rd]) = val;
+        *((uint32_t *)&env->fpr[rd]) = helper_ld_asi(addr, asi, size, 0);
         break;
     case 8:
-        *((int64_t *)&DT0) = val;
+        u.ll = helper_ld_asi(addr, asi, size, 0);
+        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
+        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
         break;
     case 16:
-        // XXX
+        u.ll = helper_ld_asi(addr, asi, 8, 0);
+        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
+        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
+        u.ll = helper_ld_asi(addr + 8, asi, 8, 0);
+        *((uint32_t *)&env->fpr[rd++]) = u.l.upper;
+        *((uint32_t *)&env->fpr[rd++]) = u.l.lower;
         break;
     }
 }
-- 
1.7.5.4

[Qemu-devel] [PATCH v2 2/8] SPARC64: fp_disabled checks on ldfa/lddfa/ldqfa

[Tsuneo Saito]

ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/translate.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index f32a674..1e7e68d 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -4484,10 +4484,16 @@ static void disas_sparc_insn(DisasContext * dc)
                 case 0x2d: /* V9 prefetch, no effect */
                     goto skip_move;
                 case 0x30: /* V9 ldfa */
+                    if (gen_trap_ifnofpu(dc, cpu_cond)) {
+                        goto jmp_insn;
+                    }
                     save_state(dc, cpu_cond);
                     gen_ldf_asi(cpu_addr, insn, 4, rd);
                     goto skip_move;
                 case 0x33: /* V9 lddfa */
+                    if (gen_trap_ifnofpu(dc, cpu_cond)) {
+                        goto jmp_insn;
+                    }
                     save_state(dc, cpu_cond);
                     gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
                     goto skip_move;
@@ -4495,6 +4501,9 @@ static void disas_sparc_insn(DisasContext * dc)
                     goto skip_move;
                 case 0x32: /* V9 ldqfa */
                     CHECK_FPU_FEATURE(dc, FLOAT128);
+                    if (gen_trap_ifnofpu(dc, cpu_cond)) {
+                        goto jmp_insn;
+                    }
                     save_state(dc, cpu_cond);
                     gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
                     goto skip_move;
-- 
1.7.5.4

[Qemu-devel] [PATCH v2 3/8] SPARC64: Implement stfa/stdfa/stqfa instrcutions properly

[Tsuneo Saito]

This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/op_helper.c |   15 +++++++++++----
 target-sparc/translate.c |    2 --
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index a75ac4f..fe71829 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -3396,6 +3396,7 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
 {
     unsigned int i;
     target_ulong val = 0;
+    CPU_DoubleU u;
 
     helper_check_align(addr, 3);
     addr = asi_address_mask(env, asi, addr);
@@ -3440,16 +3441,22 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
     switch(size) {
     default:
     case 4:
-        val = *((uint32_t *)&env->fpr[rd]);
+        helper_st_asi(addr, *(uint32_t *)&env->fpr[rd], asi, size);
         break;
     case 8:
-        val = *((int64_t *)&DT0);
+        u.l.upper = *(uint32_t *)&env->fpr[rd++];
+        u.l.lower = *(uint32_t *)&env->fpr[rd++];
+        helper_st_asi(addr, u.ll, asi, size);
         break;
     case 16:
-        // XXX
+        u.l.upper = *(uint32_t *)&env->fpr[rd++];
+        u.l.lower = *(uint32_t *)&env->fpr[rd++];
+        helper_st_asi(addr, u.ll, asi, 8);
+        u.l.upper = *(uint32_t *)&env->fpr[rd++];
+        u.l.lower = *(uint32_t *)&env->fpr[rd++];
+        helper_st_asi(addr + 8, u.ll, asi, 8);
         break;
     }
-    helper_st_asi(addr, val, asi, size);
 }
 
 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 1e7e68d..a5a8eaf 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -4742,12 +4742,10 @@ static void disas_sparc_insn(DisasContext * dc)
                         r_const = tcg_const_i32(7);
                         gen_helper_check_align(cpu_addr, r_const);
                         tcg_temp_free_i32(r_const);
-                        gen_op_load_fpr_QT0(QFPREG(rd));
                         gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
                     }
                     break;
                 case 0x37: /* V9 stdfa */
-                    gen_op_load_fpr_DT0(DFPREG(rd));
                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
                     break;
                 case 0x3c: /* V9 casa */
-- 
1.7.5.4

[Qemu-devel] [PATCH v2 4/8] SPARC64: fp_disabled checks on stfa/stdfa/stqfa

[Tsuneo Saito]

stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/translate.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index a5a8eaf..5f92dbb 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -4732,6 +4732,9 @@ static void disas_sparc_insn(DisasContext * dc)
                 switch (xop) {
 #ifdef TARGET_SPARC64
                 case 0x34: /* V9 stfa */
+                    if (gen_trap_ifnofpu(dc, cpu_cond)) {
+                        goto jmp_insn;
+                    }
                     gen_stf_asi(cpu_addr, insn, 4, rd);
                     break;
                 case 0x36: /* V9 stqfa */
@@ -4739,6 +4742,9 @@ static void disas_sparc_insn(DisasContext * dc)
                         TCGv_i32 r_const;
 
                         CHECK_FPU_FEATURE(dc, FLOAT128);
+                        if (gen_trap_ifnofpu(dc, cpu_cond)) {
+                            goto jmp_insn;
+                        }
                         r_const = tcg_const_i32(7);
                         gen_helper_check_align(cpu_addr, r_const);
                         tcg_temp_free_i32(r_const);
@@ -4746,6 +4752,9 @@ static void disas_sparc_insn(DisasContext * dc)
                     }
                     break;
                 case 0x37: /* V9 stdfa */
+                    if (gen_trap_ifnofpu(dc, cpu_cond)) {
+                        goto jmp_insn;
+                    }
                     gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
                     break;
                 case 0x3c: /* V9 casa */
-- 
1.7.5.4

[Qemu-devel] [PATCH v2 5/8] SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for ldfa

[Tsuneo Saito]

Support UA2007 block load ASIs for ldfa instructions.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/op_helper.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index fe71829..b76ffb6 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -3353,6 +3353,10 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
         }
 
         return;
+    case 0x16: /* UA2007 Block load primary, user privilege */
+    case 0x17: /* UA2007 Block load secondary, user privilege */
+    case 0x1e: /* UA2007 Block load primary LE, user privilege */
+    case 0x1f: /* UA2007 Block load secondary LE, user privilege */
     case 0x70: // Block load primary, user privilege
     case 0x71: // Block load secondary, user privilege
         if (rd & 7) {
@@ -3361,7 +3365,7 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
         }
         helper_check_align(addr, 0x3f);
         for (i = 0; i < 16; i++) {
-            *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x1f, 4,
+            *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x19, 4,
                                                          0);
             addr += 4;
         }
-- 
1.7.5.4

[Qemu-devel] [PATCH v2 6/8] SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for stfa

[Tsuneo Saito]

Support UA2007 block store ASIs for stfa instructions.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/op_helper.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index b76ffb6..4faa709 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -3424,6 +3424,10 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
         }
 
         return;
+    case 0x16: /* UA2007 Block load primary, user privilege */
+    case 0x17: /* UA2007 Block load secondary, user privilege */
+    case 0x1e: /* UA2007 Block load primary LE, user privilege */
+    case 0x1f: /* UA2007 Block load secondary LE, user privilege */
     case 0x70: // Block store primary, user privilege
     case 0x71: // Block store secondary, user privilege
         if (rd & 7) {
@@ -3433,7 +3437,7 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
         helper_check_align(addr, 0x3f);
         for (i = 0; i < 16; i++) {
             val = *(uint32_t *)&env->fpr[rd++];
-            helper_st_asi(addr, val, asi & 0x1f, 4);
+            helper_st_asi(addr, val, asi & 0x19, 4);
             addr += 4;
         }
 
-- 
1.7.5.4

[Qemu-devel] [PATCH v2 7/8] SPARC64: Add JPS1 ASI_BLK_AIU[PS]L ASIs for ldfa and stfa

[Tsuneo Saito]

Support JPS1 little endian block transfer ASIs.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/op_helper.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 4faa709..2a28d5f 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -3359,6 +3359,8 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
     case 0x1f: /* UA2007 Block load secondary LE, user privilege */
     case 0x70: // Block load primary, user privilege
     case 0x71: // Block load secondary, user privilege
+    case 0x78: /* JPS1 Block load primary LE, user privilege */
+    case 0x79: /* JPS1 Block load secondary LE, user privilege */
         if (rd & 7) {
             raise_exception(TT_ILL_INSN);
             return;
@@ -3430,6 +3432,8 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
     case 0x1f: /* UA2007 Block load secondary LE, user privilege */
     case 0x70: // Block store primary, user privilege
     case 0x71: // Block store secondary, user privilege
+    case 0x78: /* JPS1 Block load primary LE, user privilege */
+    case 0x79: /* JPS1 Block load secondary LE, user privilege */
         if (rd & 7) {
             raise_exception(TT_ILL_INSN);
             return;
-- 
1.7.5.4

[Qemu-devel] [PATCH v2 8/8] SPARC64: C99 comment fix for block-transfer ASIs

[Tsuneo Saito]

Fixed C99 comments on block-tranfer ASIs.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
 target-sparc/op_helper.c |   28 ++++++++++++++--------------
 1 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 2a28d5f..15af27b 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -3337,10 +3337,10 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
     addr = asi_address_mask(env, asi, addr);
 
     switch (asi) {
-    case 0xf0: // Block load primary
-    case 0xf1: // Block load secondary
-    case 0xf8: // Block load primary LE
-    case 0xf9: // Block load secondary LE
+    case 0xf0: /* UA2007/JPS1 Block load primary */
+    case 0xf1: /* UA2007/JPS1 Block load secondary */
+    case 0xf8: /* UA2007/JPS1 Block load primary LE */
+    case 0xf9: /* UA2007/JPS1 Block load secondary LE */
         if (rd & 7) {
             raise_exception(TT_ILL_INSN);
             return;
@@ -3357,8 +3357,8 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
     case 0x17: /* UA2007 Block load secondary, user privilege */
     case 0x1e: /* UA2007 Block load primary LE, user privilege */
     case 0x1f: /* UA2007 Block load secondary LE, user privilege */
-    case 0x70: // Block load primary, user privilege
-    case 0x71: // Block load secondary, user privilege
+    case 0x70: /* JPS1 Block load primary, user privilege */
+    case 0x71: /* JPS1 Block load secondary, user privilege */
     case 0x78: /* JPS1 Block load primary LE, user privilege */
     case 0x79: /* JPS1 Block load secondary LE, user privilege */
         if (rd & 7) {
@@ -3408,12 +3408,12 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
     addr = asi_address_mask(env, asi, addr);
 
     switch (asi) {
-    case 0xe0: // UA2007 Block commit store primary (cache flush)
-    case 0xe1: // UA2007 Block commit store secondary (cache flush)
-    case 0xf0: // Block store primary
-    case 0xf1: // Block store secondary
-    case 0xf8: // Block store primary LE
-    case 0xf9: // Block store secondary LE
+    case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
+    case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
+    case 0xf0: /* UA2007/JPS1 Block store primary */
+    case 0xf1: /* UA2007/JPS1 Block store secondary */
+    case 0xf8: /* UA2007/JPS1 Block store primary LE */
+    case 0xf9: /* UA2007/JPS1 Block store secondary LE */
         if (rd & 7) {
             raise_exception(TT_ILL_INSN);
             return;
@@ -3430,8 +3430,8 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
     case 0x17: /* UA2007 Block load secondary, user privilege */
     case 0x1e: /* UA2007 Block load primary LE, user privilege */
     case 0x1f: /* UA2007 Block load secondary LE, user privilege */
-    case 0x70: // Block store primary, user privilege
-    case 0x71: // Block store secondary, user privilege
+    case 0x70: /* JPS1 Block store primary, user privilege */
+    case 0x71: /* JPS1 Block store secondary, user privilege */
     case 0x78: /* JPS1 Block load primary LE, user privilege */
     case 0x79: /* JPS1 Block load secondary LE, user privilege */
         if (rd & 7) {
-- 
1.7.5.4

Re: [Qemu-devel] [PATCH v2 4/8] SPARC64: fp_disabled checks on stfa/stdfa/stqfa

[Peter Maydell]

On 14 July 2011 10:41, Tsuneo Saito <tsnsaito@gmail.com> wrote:
> stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
> if %pstate.PEF==0 or %fprs.FEF==0.

Not really related to this patch but I happened to notice it:
we generate a trap if dc->fpu_enabled is clear. That flag is set with:
        dc->fpu_enabled = cpu_fpu_enabled(env);
which looks at the CPUState passed into gen_intermediate_code_internal.

I think it should be pulling the fpu-enabled state out of the
tb->flags instead. Otherwise you'll have problems if you have
a TB with (1) a trap-if-no-fpu insn (2) a change of the fpu-enabled
state (3) a load/store that faults.

-- PMM

Re: [Qemu-devel] [PATCH v2 4/8] SPARC64: fp_disabled checks on stfa/stdfa/stqfa

[Blue Swirl]

On Thu, Jul 14, 2011 at 1:39 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 14 July 2011 10:41, Tsuneo Saito <tsnsaito@gmail.com> wrote:
>> stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
>> if %pstate.PEF==0 or %fprs.FEF==0.
>
> Not really related to this patch but I happened to notice it:
> we generate a trap if dc->fpu_enabled is clear. That flag is set with:
>        dc->fpu_enabled = cpu_fpu_enabled(env);
> which looks at the CPUState passed into gen_intermediate_code_internal.
>
> I think it should be pulling the fpu-enabled state out of the
> tb->flags instead. Otherwise you'll have problems if you have
> a TB with (1) a trap-if-no-fpu insn (2) a change of the fpu-enabled
> state (3) a load/store that faults.

Nice catch, this also affects Sparc32.

Re: [Qemu-devel] [PATCH v2 0/8] SPARC64: Implement sparcv9 ldfa/stfa instructions

[Blue Swirl]

Thanks, applied all.

On Thu, Jul 14, 2011 at 12:41 PM, Tsuneo Saito <tsnsaito@gmail.com> wrote:
> This patch series implements sparcv9 stfa/ldfa instructions that
> implementations seem to be left unfinished.
> This patch also adds fp_disabled exception checks on stfa/ldfa
> as they are FP instructions.
>
> v2:
>  * checked by checkpatch.pl.
>  * added UA2007 block-transfer ASIs.
>  * added JPS1 little-endian block-transfer ASIs that seem forgotten.
>
>  target-sparc/op_helper.c |   75 ++++++++++++++++++++++++++++++---------------
>  target-sparc/translate.c |   20 +++++++++++-
>  2 files changed, 68 insertions(+), 27 deletions(-)
>
> --
> 1.7.5.4
>
>
>

Re: [Qemu-devel] [PATCH v2 4/8] SPARC64: fp_disabled checks on stfa/stdfa/stqfa

[Blue Swirl]

On Thu, Jul 14, 2011 at 1:39 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 14 July 2011 10:41, Tsuneo Saito <tsnsaito@gmail.com> wrote:
>> stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
>> if %pstate.PEF==0 or %fprs.FEF==0.
>
> Not really related to this patch but I happened to notice it:
> we generate a trap if dc->fpu_enabled is clear. That flag is set with:
>        dc->fpu_enabled = cpu_fpu_enabled(env);
> which looks at the CPUState passed into gen_intermediate_code_internal.
>
> I think it should be pulling the fpu-enabled state out of the
> tb->flags instead. Otherwise you'll have problems if you have
> a TB with (1) a trap-if-no-fpu insn (2) a change of the fpu-enabled
> state (3) a load/store that faults.

I applied a patch to fix this and similar bug with AM bit.

Re: [Qemu-devel] [PATCH v2 6/8] SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for stfa

[Artyom Tarasenko]

On Thu, Jul 14, 2011 at 11:41 AM, Tsuneo Saito <tsnsaito@gmail.com> wrote:
> Support UA2007 block store ASIs for stfa instructions.
>
> Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
> ---
>  target-sparc/op_helper.c |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)
>
> diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
> index b76ffb6..4faa709 100644
> --- a/target-sparc/op_helper.c
> +++ b/target-sparc/op_helper.c
> @@ -3424,6 +3424,10 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
>         }
>
>         return;
> +    case 0x16: /* UA2007 Block load primary, user privilege */
> +    case 0x17: /* UA2007 Block load secondary, user privilege */
> +    case 0x1e: /* UA2007 Block load primary LE, user privilege */
> +    case 0x1f: /* UA2007 Block load secondary LE, user privilege */

shouldn't these be added to the list in is_translating_asi() ?

>     case 0x70: // Block store primary, user privilege
>     case 0x71: // Block store secondary, user privilege
>         if (rd & 7) {
> @@ -3433,7 +3437,7 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
>         helper_check_align(addr, 0x3f);
>         for (i = 0; i < 16; i++) {
>             val = *(uint32_t *)&env->fpr[rd++];
> -            helper_st_asi(addr, val, asi & 0x1f, 4);
> +            helper_st_asi(addr, val, asi & 0x19, 4);
>             addr += 4;
>         }
>
> --
> 1.7.5.4
>
>
>



-- 
Regards,
Artyom Tarasenko

solaris/sparc under qemu blog: http://tyom.blogspot.com/

Re: [Qemu-devel] [PATCH v2 6/8] SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for stfa

[tsnsaito]

At Thu, 14 Jul 2011 22:46:30 +0200,
Artyom Tarasenko wrote:
> On Thu, Jul 14, 2011 at 11:41 AM, Tsuneo Saito <tsnsaito@gmail.com> wrote:
> > Support UA2007 block store ASIs for stfa instructions.
> >
> > Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
> > ---
> >  target-sparc/op_helper.c |    6 +++++-
> >  1 files changed, 5 insertions(+), 1 deletions(-)
> >
> > diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
> > index b76ffb6..4faa709 100644
> > --- a/target-sparc/op_helper.c
> > +++ b/target-sparc/op_helper.c
> > @@ -3424,6 +3424,10 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
> >         }
> >
> >         return;
> > +    case 0x16: /* UA2007 Block load primary, user privilege */
> > +    case 0x17: /* UA2007 Block load secondary, user privilege */
> > +    case 0x1e: /* UA2007 Block load primary LE, user privilege */
> > +    case 0x1f: /* UA2007 Block load secondary LE, user privilege */
> 
> shouldn't these be added to the list in is_translating_asi() ?

Ah yes, that's right!

---- 
Tsuneo Saito <tsnsaito@gmail.com>