From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:52243) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qji3M-0002DB-2M for qemu-devel@nongnu.org; Wed, 20 Jul 2011 21:28:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qji3A-0003ri-Pc for qemu-devel@nongnu.org; Wed, 20 Jul 2011 21:27:51 -0400 Received: from cantor2.suse.de ([195.135.220.15]:58002 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qji39-0003qU-0i for qemu-devel@nongnu.org; Wed, 20 Jul 2011 21:27:39 -0400 From: Alexander Graf Date: Thu, 21 Jul 2011 03:27:21 +0200 Message-Id: <1311211654-14326-11-git-send-email-agraf@suse.de> In-Reply-To: <1311211654-14326-1-git-send-email-agraf@suse.de> References: <1311211654-14326-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 10/23] PPC: E500: Generate IRQ lines for many CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU-devel Developers Cc: Scott Wood Now that we can generate multiple envs for all our virtual CPUs, we also need to tell the MPIC that we have multiple CPUs connected and connect them all to the respective virtual interrupt lines. Signed-off-by: Alexander Graf --- hw/ppce500_mpc8544ds.c | 17 ++++++++++++----- 1 files changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index cefb415..7ce9bc7 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -237,7 +237,7 @@ static void mpc8544ds_init(ram_addr_t ram_size, target_long initrd_size=0; int i=0; unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; - qemu_irq *irqs, *mpic; + qemu_irq **irqs, *mpic; DeviceState *dev; struct boot_info *boot_info; CPUState *firstenv = NULL; @@ -247,6 +247,8 @@ static void mpc8544ds_init(ram_addr_t ram_size, cpu_model = "e500v2_v30"; } + irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); + irqs[0] = qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); for (i = 0; i < smp_cpus; i++) { qemu_irq *input; env = cpu_ppc_init(cpu_model); @@ -259,6 +261,10 @@ static void mpc8544ds_init(ram_addr_t ram_size, firstenv = env; } + irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); + input = (qemu_irq *)env->irq_inputs; + irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; + irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; /* XXX register timer? */ @@ -283,10 +289,11 @@ static void mpc8544ds_init(ram_addr_t ram_size, "mpc8544ds.ram", ram_size)); /* MPIC */ - irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); - irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT]; - irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT]; - mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL); + mpic = mpic_init(MPC8544_MPIC_REGS_BASE, smp_cpus, irqs, NULL); + + if (!mpic) { + cpu_abort(env, "MPIC failed to initialize\n"); + } /* Serial */ if (serial_hds[0]) { -- 1.6.0.2