From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:52167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qji3H-0002CU-2v for qemu-devel@nongnu.org; Wed, 20 Jul 2011 21:27:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qji39-0003r0-SS for qemu-devel@nongnu.org; Wed, 20 Jul 2011 21:27:46 -0400 Received: from cantor2.suse.de ([195.135.220.15]:58000 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qji38-0003q7-W5 for qemu-devel@nongnu.org; Wed, 20 Jul 2011 21:27:39 -0400 From: Alexander Graf Date: Thu, 21 Jul 2011 03:27:18 +0200 Message-Id: <1311211654-14326-8-git-send-email-agraf@suse.de> In-Reply-To: <1311211654-14326-1-git-send-email-agraf@suse.de> References: <1311211654-14326-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 07/23] PPC: Remove cINT code from MPIC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU-devel Developers Cc: Scott Wood The current code treats some bits in IDE as special for critical interrupts. While there is logic to route interrupts as critical, that happens through a different register. So for now I'm just removing the check to enable up to 32 virtual CPUs. Signed-off-by: Alexander Graf --- hw/openpic.c | 9 +-------- 1 files changed, 1 insertions(+), 8 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 08a3a65..6630206 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -1278,14 +1278,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src) { - int n_ci = IDR_CI0 - n_CPU; - - if(test_bit(&src->ide, n_ci)) { - qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]); - } - else { - qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); - } + qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); } static void mpic_reset (void *opaque) -- 1.6.0.2