[Qemu-devel] [PATCH 00/23] SMP support for MPC8544DS

[Qemu-devel] [PATCH 00/23] SMP support for MPC8544DS

[Alexander Graf]

Due to popular demand, I got involved in the dirty arts of SMP
programming :). This patch set adds support for the MPC8544DS board
(e500v2) to run with up to 32 virtual CPUs.

This works fine with emulation and Linux guests. It also works with
KVM when disabling the DEC trick in ppc_spin.c - something seems to
be broken in KVM there.

For non-Linux guests, TLB invalidation broadcasting is still missing,
but for now this is enough to get Linux up and running.

I've used the chance while touching the code to also clean up ugly
code that just diverged over time between the 3 KVM capable PPC
targets (frequency device-tree entries). They're intertwined with
this series, but I hope not too hard to understand, so they don't
hurt being there.

Alexander Graf (23):
  PPC: Add secondary CPU spinning code
  PPC: Move openpic to target specific code compilation
  PPC: Add CPU definitions for up to 32 guest CPUs
  PPC: Add CPU local MMIO regions to MPIC
  PPC: Extend MPIC MMIO range
  PPC: Fix IPI support in MPIC
  PPC: Remove cINT code from MPIC
  PPC: Bump MPIC up to 32 supported CPUs
  PPC: E500: create multiple envs
  PPC: E500: Generate IRQ lines for many CPUs
  PPC: E500: Use spin code for secondary CPUs
  device tree: add nop_node
  PPC: bamboo: Move host fdt copy to target
  PPC: KVM: Add generic function to read host clockfreq
  PPC: E500: Use generic kvm function for freq
  PPC: E500: Remove mpc8544_copy_soc_cell
  PPC: bamboo: Use kvm api for freq and clock frequencies
  PPC: KVM: Remove kvmppc_read_host_property
  PPC: KVM: Add stubs for kvm helper functions
  PPC: E500: Update freqs for all CPUs
  PPC: E500: Remove unneeded CPU nodes
  PPC: E500: Update cpu-release-addr property in cpu nodes
  PPC: E500: Bump CPU count to 32

 Makefile.objs          |    1 -
 Makefile.target        |    2 +
 device_tree.c          |   11 ++
 device_tree.h          |    1 +
 hw/openpic.c           |  148 ++++++++++------
 hw/ppc440_bamboo.c     |   16 ++-
 hw/ppce500_mpc8544ds.c |  159 +++++++++---------
 pc-bios/mpc8544ds.dtb  |  Bin 2277 -> 9699 bytes
 pc-bios/mpc8544ds.dts  |  437 ++++++++++++++++++++++++++++++++++++++++++++++++
 pc-bios/ppc_spin.c     |   97 +++++++++++
 pc-bios/ppc_spin.elf   |  Bin 0 -> 66553 bytes
 target-ppc/kvm.c       |   65 +++++++
 target-ppc/kvm_ppc.c   |   65 -------
 target-ppc/kvm_ppc.h   |   39 +++--
 14 files changed, 823 insertions(+), 218 deletions(-)
 create mode 100644 pc-bios/ppc_spin.c
 create mode 100755 pc-bios/ppc_spin.elf

[Qemu-devel] [PATCH 01/23] PPC: Add secondary CPU spinning code

[Alexander Graf]

When directly starting an SMP system with -kernel on PPC e500, we need to
simulate the spin table code from u-boot. This code adds a small c file
plus generated .elf file that enable secondary CPUs to spin just like they
would with u-boot.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 pc-bios/ppc_spin.c   |   97 ++++++++++++++++++++++++++++++++++++++++++++++++++
 pc-bios/ppc_spin.elf |  Bin 0 -> 66553 bytes
 2 files changed, 97 insertions(+), 0 deletions(-)
 create mode 100644 pc-bios/ppc_spin.c
 create mode 100755 pc-bios/ppc_spin.elf

diff --git a/pc-bios/ppc_spin.c b/pc-bios/ppc_spin.c
new file mode 100644
index 0000000..e46a6a7
--- /dev/null
+++ b/pc-bios/ppc_spin.c
@@ -0,0 +1,97 @@
+#include <stdio.h>
+#include <stdint.h>
+
+/*
+ * Secondary CPU spin code
+ *
+ * Compile using: gcc -m32 -nostdlib ppc_spin.c -o ppc_spin.elf -Os \
+ *                    -fno-stack-protector -Wl,-Ttext,0x7700000
+ */
+
+/* Initialize stack pointer */
+asm (
+"    .global _start             \n"
+"    _start:                    \n"
+"    addis   1, 3, 0x10000@h    \n"
+"    b       spin               \n");
+
+typedef struct spin_info {
+    uint32_t addr_hi;
+    uint32_t addr;
+    uint32_t r3_hi;
+    uint32_t r3;
+    uint32_t resv;
+    uint32_t pir;
+    uint32_t r6_hi;
+    uint32_t r6;
+} SpinInfo;
+
+#define __stringify_1(x...)     #x
+#define __stringify(x...)       __stringify_1(x)
+
+#define mfspr(rn)       ({unsigned long rval; \
+                        asm volatile("mfspr %0," __stringify(rn) \
+                                : "=r" (rval)); rval;})
+#define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)\
+                                     : "memory")
+static inline void mtdec(unsigned long v)
+{
+    asm volatile("mtdec %0" : : "r" (v));
+}
+
+static inline void mtmsr(unsigned long msr)
+{
+    asm("mtmsr %0" : : "r"(msr));
+}
+
+#define __MASK(X)        (1UL<<(X))
+#define MSR_WE_LG        18              /* Wait State Enable */
+#define MSR_EE_LG        15              /* External Interrupt Enable */
+#define MSR_WE           __MASK(MSR_WE_LG)       /* Wait State Enable */
+#define MSR_EE           __MASK(MSR_EE_LG)       /* External Interrupt Enable */
+#define SPR_PIR          0x11E
+#define SPR_HID0         (0x3F0)
+#define SPR_BOOKE_IVOR10 (0x19A)
+#define SPR_BOOKE_IVPR   (0x03F)
+
+void loop(void);
+
+__attribute__((noreturn)) void spin(unsigned long ptr)
+{
+    volatile SpinInfo *info = (void*)ptr;
+    uint32_t pir = mfspr(SPR_PIR);
+    __attribute__((noreturn)) void (*entry)(
+        unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6,
+        unsigned long r7, unsigned long r8, unsigned long r9);
+    unsigned long dec_p = (unsigned long)loop;
+
+    info->pir = pir;
+    info->r3 = pir;
+    info->addr = 1;
+    info->r6 = 0;
+
+    /* we don't want to keep the other CPUs from running, so set the IVOR for
+       DEC to our loop and only check for info->addr every other cycle */
+
+    mtspr(SPR_HID0, 0x00E00000);
+    mtspr(SPR_BOOKE_IVOR10, dec_p & 0xfff);
+    mtspr(SPR_BOOKE_IVPR, dec_p & ~0xfff);
+loop:
+    asm volatile (".global loop\n"
+        "   loop:" : : : "memory", "cc");
+
+    if (info->addr & 1) {
+        /* wait until addr is valid */
+        mtdec(0x100000);
+        mtmsr(MSR_WE|MSR_EE);
+        /* should never reach here */
+        while(1) { }
+    }
+
+    asm volatile ("");
+
+    mtspr(SPR_HID0, 0);
+    info->pir = pir;
+    entry = (void*)(unsigned long)info->addr;
+    entry(info->r3, 0, 0, info->r6, 64 * 1024 * 1024, 0, 0);
+}
diff --git a/pc-bios/ppc_spin.elf b/pc-bios/ppc_spin.elf
new file mode 100755
index 0000000000000000000000000000000000000000..71c872b2d4685100b0050d549735662d7d763e08
GIT binary patch
literal 66553
zcmeIvJ#14~6u|Lw?Uy)KGdMIt2pAq}1Q;n#1dNoR(27QsO65DrK&xW>rNk<+U+tGR
zRgG$Ot}0q}>d-PEFED0dXJcVxWa(Zcm>A4Cetr(1EQs}gt>bs@Irqcw=U>iU_`;=}
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zr;Vso)@Rg;pX*5$)wUuD8qKH{=+2<LS-(}Ctyd+eG&eSC4eeRE6h*Cic{8fDM~%RK
zU~u`$N?R{`k8wcP+V30Bgu_ha!5jO{$A+0@G*UT{ZQZf0`HV&~l63_w*m?1A@>G-4
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literal 0
HcmV?d00001

-- 
1.6.0.2

[Qemu-devel] [PATCH 02/23] PPC: Move openpic to target specific code compilation

[Alexander Graf]

The MPIC has some funny feature where it maps different registers to an MMIO
region depending which CPU accesses them.

To be able to reflect that, we need to make OpenPIC be compiled in the target
code, so it can access cpu_single_env.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 Makefile.objs   |    1 -
 Makefile.target |    2 ++
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/Makefile.objs b/Makefile.objs
index c43ed05..6ab8247 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -207,7 +207,6 @@ hw-obj-$(CONFIG_SMARTCARD) += usb-ccid.o ccid-card-passthru.o
 hw-obj-$(CONFIG_SMARTCARD_NSS) += ccid-card-emulated.o
 
 # PPC devices
-hw-obj-$(CONFIG_OPENPIC) += openpic.o
 hw-obj-$(CONFIG_PREP_PCI) += prep_pci.o
 # Mac shared devices
 hw-obj-$(CONFIG_MACIO) += macio.o
diff --git a/Makefile.target b/Makefile.target
index e20a313..0568d05 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -255,6 +255,8 @@ obj-ppc-y += ppce500_mpc8544ds.o mpc8544_guts.o
 obj-ppc-y += virtex_ml507.o
 obj-ppc-$(CONFIG_KVM) += kvm_ppc.o
 obj-ppc-$(CONFIG_FDT) += device_tree.o
+# PowerPC OpenPIC
+obj-ppc-y += openpic.o
 
 # Xilinx PPC peripherals
 obj-ppc-y += xilinx_intc.o
-- 
1.6.0.2

[Qemu-devel] [PATCH 03/23] PPC: Add CPU definitions for up to 32 guest CPUs

[Alexander Graf]

All guest CPUs need to be specified in the device trees. Since removing nodes
is easy with FDT, but adding nodes is not, we just put 32 CPU nodes into the
device tree and remove them later on init when not used.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 pc-bios/mpc8544ds.dtb |  Bin 2277 -> 9699 bytes
 pc-bios/mpc8544ds.dts |  437 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 437 insertions(+), 0 deletions(-)

diff --git a/pc-bios/mpc8544ds.dtb b/pc-bios/mpc8544ds.dtb
index ae318b1fe83846cc2e133951a3666fcfcdf87f79..18667f87588e390018149e548468e1a119433eea 100644
GIT binary patch
literal 9699
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diff --git a/pc-bios/mpc8544ds.dts b/pc-bios/mpc8544ds.dts
index a88b47c..b127992 100644
--- a/pc-bios/mpc8544ds.dts
+++ b/pc-bios/mpc8544ds.dts
@@ -36,6 +36,443 @@
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@1 {
+			device_type = "cpu";
+			reg = <0x1>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@2 {
+			device_type = "cpu";
+			reg = <0x2>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@3 {
+			device_type = "cpu";
+			reg = <0x3>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@4 {
+			device_type = "cpu";
+			reg = <0x4>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@5 {
+			device_type = "cpu";
+			reg = <0x5>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@6 {
+			device_type = "cpu";
+			reg = <0x6>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@7 {
+			device_type = "cpu";
+			reg = <0x7>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@8 {
+			device_type = "cpu";
+			reg = <0x8>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@9 {
+			device_type = "cpu";
+			reg = <0x9>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@a {
+			device_type = "cpu";
+			reg = <0xa>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@b {
+			device_type = "cpu";
+			reg = <0xb>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@c {
+			device_type = "cpu";
+			reg = <0xc>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@d {
+			device_type = "cpu";
+			reg = <0xd>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@e {
+			device_type = "cpu";
+			reg = <0xe>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@f {
+			device_type = "cpu";
+			reg = <0xf>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@10 {
+			device_type = "cpu";
+			reg = <0x10>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@11 {
+			device_type = "cpu";
+			reg = <0x11>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@12 {
+			device_type = "cpu";
+			reg = <0x12>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@13 {
+			device_type = "cpu";
+			reg = <0x13>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@14 {
+			device_type = "cpu";
+			reg = <0x14>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@15 {
+			device_type = "cpu";
+			reg = <0x15>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@16 {
+			device_type = "cpu";
+			reg = <0x16>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@17 {
+			device_type = "cpu";
+			reg = <0x17>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@18 {
+			device_type = "cpu";
+			reg = <0x18>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@19 {
+			device_type = "cpu";
+			reg = <0x19>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@1a {
+			device_type = "cpu";
+			reg = <0x1a>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@1b {
+			device_type = "cpu";
+			reg = <0x1b>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@1c {
+			device_type = "cpu";
+			reg = <0x1c>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@1d {
+			device_type = "cpu";
+			reg = <0x1d>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@1e {
+			device_type = "cpu";
+			reg = <0x1e>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
+		};
+		PowerPC,8544@1f {
+			device_type = "cpu";
+			reg = <0x1f>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			status = "disabled";
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>;
 		};
 	};
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 04/23] PPC: Add CPU local MMIO regions to MPIC

[Alexander Graf]

The MPIC exports a register set for each CPU connected to it. They can all
be accessed through specific registers or using a shadow page that is mapped
differently depending on which CPU accesses it.

This patch implements the shadow map, making it possible for guests to access
the CPU local registers using the same address on each CPU.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |  110 ++++++++++++++++++++++++++++++++++++++--------------------
 1 files changed, 72 insertions(+), 38 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 6d2cf99..491bfee 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -2,6 +2,7 @@
  * OpenPIC emulation
  *
  * Copyright (c) 2004 Jocelyn Mayer
+ *               2011 Alexander Graf
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -161,6 +162,16 @@ static inline int test_bit (uint32_t *field, int bit)
     return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0;
 }
 
+static int get_current_cpu(void)
+{
+  return cpu_single_env->cpu_index;
+}
+
+static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
+                                          int idx);
+static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
+                                       uint32_t val, int idx);
+
 enum {
     IRQ_EXTERNAL = 0x01,
     IRQ_INTERNAL = 0x02,
@@ -590,18 +601,27 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
     DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
     if (addr & 0xF)
         return;
-    addr &= 0xFF;
     switch (addr) {
-    case 0x00: /* FREP */
+    case 0x40:
+    case 0x50:
+    case 0x60:
+    case 0x70:
+    case 0x80:
+    case 0x90:
+    case 0xA0:
+    case 0xB0:
+        openpic_cpu_write_internal(opp, addr, val, get_current_cpu());
+        break;
+    case 0x1000: /* FREP */
         break;
-    case 0x20: /* GLBC */
+    case 0x1020: /* GLBC */
         if (val & 0x80000000 && opp->reset)
             opp->reset(opp);
         opp->glbc = val & ~0x80000000;
         break;
-    case 0x80: /* VENI */
+    case 0x1080: /* VENI */
         break;
-    case 0x90: /* PINT */
+    case 0x1090: /* PINT */
         for (idx = 0; idx < opp->nb_cpus; idx++) {
             if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) {
                 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
@@ -615,22 +635,20 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
         }
         opp->pint = val;
         break;
-#if MAX_IPI > 0
-    case 0xA0: /* IPI_IPVP */
-    case 0xB0:
-    case 0xC0:
-    case 0xD0:
+    case 0x10A0: /* IPI_IPVP */
+    case 0x10B0:
+    case 0x10C0:
+    case 0x10D0:
         {
             int idx;
-            idx = (addr - 0xA0) >> 4;
+            idx = (addr - 0x10A0) >> 4;
             write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP, val);
         }
         break;
-#endif
-    case 0xE0: /* SPVE */
+    case 0x10E0: /* SPVE */
         opp->spve = val & 0x000000FF;
         break;
-    case 0xF0: /* TIFR */
+    case 0x10F0: /* TIFR */
         opp->tifr = val;
         break;
     default:
@@ -647,36 +665,43 @@ static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
     retval = 0xFFFFFFFF;
     if (addr & 0xF)
         return retval;
-    addr &= 0xFF;
     switch (addr) {
-    case 0x00: /* FREP */
+    case 0x1000: /* FREP */
         retval = opp->frep;
         break;
-    case 0x20: /* GLBC */
+    case 0x1020: /* GLBC */
         retval = opp->glbc;
         break;
-    case 0x80: /* VENI */
+    case 0x1080: /* VENI */
         retval = opp->veni;
         break;
-    case 0x90: /* PINT */
+    case 0x1090: /* PINT */
         retval = 0x00000000;
         break;
-#if MAX_IPI > 0
-    case 0xA0: /* IPI_IPVP */
+    case 0x40:
+    case 0x50:
+    case 0x60:
+    case 0x70:
+    case 0x80:
+    case 0x90:
+    case 0xA0:
     case 0xB0:
-    case 0xC0:
-    case 0xD0:
+        retval = openpic_cpu_read_internal(opp, addr, get_current_cpu());
+        break;
+    case 0x10A0: /* IPI_IPVP */
+    case 0x10B0:
+    case 0x10C0:
+    case 0x10D0:
         {
             int idx;
-            idx = (addr - 0xA0) >> 4;
+            idx = (addr - 0x10A0) >> 4;
             retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP);
         }
         break;
-#endif
-    case 0xE0: /* SPVE */
+    case 0x10E0: /* SPVE */
         retval = opp->spve;
         break;
-    case 0xF0: /* TIFR */
+    case 0x10F0: /* TIFR */
         retval = opp->tifr;
         break;
     default:
@@ -794,23 +819,23 @@ static uint32_t openpic_src_read (void *opaque, uint32_t addr)
     return retval;
 }
 
-static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t val)
+static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
+                                       uint32_t val, int idx)
 {
     openpic_t *opp = opaque;
     IRQ_src_t *src;
     IRQ_dst_t *dst;
-    int idx, s_IRQ, n_IRQ;
+    int s_IRQ, n_IRQ;
 
-    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
+    DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx,
+            addr, val);
     if (addr & 0xF)
         return;
-    addr &= 0x1FFF0;
-    idx = addr / 0x1000;
     dst = &opp->dst[idx];
     addr &= 0xFF0;
     switch (addr) {
 #if MAX_IPI > 0
-    case 0x40: /* PIPD */
+    case 0x40: /* IPIDR */
     case 0x50:
     case 0x60:
     case 0x70:
@@ -852,20 +877,24 @@ static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t v
     }
 }
 
-static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
+static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+    openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
+}
+
+static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
+                                          int idx)
 {
     openpic_t *opp = opaque;
     IRQ_src_t *src;
     IRQ_dst_t *dst;
     uint32_t retval;
-    int idx, n_IRQ;
+    int n_IRQ;
 
-    DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
+    DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr);
     retval = 0xFFFFFFFF;
     if (addr & 0xF)
         return retval;
-    addr &= 0x1FFF0;
-    idx = addr / 0x1000;
     dst = &opp->dst[idx];
     addr &= 0xFF0;
     switch (addr) {
@@ -925,6 +954,11 @@ static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
     return retval;
 }
 
+static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr)
+{
+    return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
+}
+
 static void openpic_buggy_write (void *opaque,
                                  target_phys_addr_t addr, uint32_t val)
 {
-- 
1.6.0.2

[Qemu-devel] [PATCH 05/23] PPC: Extend MPIC MMIO range

[Alexander Graf]

The MPIC exports a page for each CPU that it controls. To support more than
one CPU, we need to also reserve the MMIO space according to the amount of
CPUs we want to support.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 491bfee..ad45331 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -128,7 +128,7 @@ enum {
 #define MPIC_MSI_REG_START        0x11C00
 #define MPIC_MSI_REG_SIZE         0x100
 #define MPIC_CPU_REG_START        0x20000
-#define MPIC_CPU_REG_SIZE         0x100
+#define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
 
 enum mpic_ide_bits {
     IDR_EP     = 0,
-- 
1.6.0.2

[Qemu-devel] [PATCH 06/23] PPC: Fix IPI support in MPIC

[Alexander Graf]

The current IPI support in the MPIC code is incomplete and doesn't work. This
code adds proper support for IPIs in MPIC by using the IDE register to remember
which CPUs IPIs are still outstanding to. New triggers through the IPI trigger
register only add to the list of CPUs we want to IPI.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   17 +++++++++++++++--
 1 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index ad45331..08a3a65 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -57,7 +57,7 @@
 #define MAX_MBX     4
 #define MAX_TMR     4
 #define VECTOR_BITS 8
-#define MAX_IPI     0
+#define MAX_IPI     4
 
 #define VID (0x00000000)
 
@@ -840,7 +840,9 @@ static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
     case 0x60:
     case 0x70:
         idx = (addr - 0x40) >> 4;
-        write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE, val);
+        /* we use IDE as mask which CPUs to deliver the IPI to still. */
+        write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE,
+                     opp->src[opp->irq_ipi0 + idx].ide | val);
         openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
         openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
         break;
@@ -934,6 +936,17 @@ static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
                 reset_bit(&src->ipvp, IPVP_ACTIVITY);
                 src->pending = 0;
             }
+
+            if ((n_IRQ >= opp->irq_ipi0) &&  (n_IRQ < (opp->irq_ipi0 + 4))) {
+                src->ide &= ~(1 << idx);
+                if (src->ide && !test_bit(&src->ipvp, IPVP_SENSE)) {
+                    /* trigger on CPUs that didn't know about it yet */
+                    openpic_set_irq(opp, n_IRQ, 1);
+                    openpic_set_irq(opp, n_IRQ, 0);
+                    /* if all CPUs knew about it, set active bit again */
+                    set_bit(&src->ipvp, IPVP_ACTIVITY);
+                }
+            }
         }
         break;
     case 0xB0: /* PEOI */
-- 
1.6.0.2

[Qemu-devel] [PATCH 07/23] PPC: Remove cINT code from MPIC

[Alexander Graf]

The current code treats some bits in IDE as special for critical interrupts.
While there is logic to route interrupts as critical, that happens through
a different register. So for now I'm just removing the check to enable up to 32
virtual CPUs.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 08a3a65..6630206 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -1278,14 +1278,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
 
 static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
 {
-    int n_ci = IDR_CI0 - n_CPU;
-
-    if(test_bit(&src->ide, n_ci)) {
-        qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
-    }
-    else {
-        qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
-    }
+    qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
 }
 
 static void mpic_reset (void *opaque)
-- 
1.6.0.2

[Qemu-devel] [PATCH 08/23] PPC: Bump MPIC up to 32 supported CPUs

[Alexander Graf]

The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in
the code exporting the numbers out and fix an integer overflow while at it.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   10 +++-------
 1 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 6630206..a8d7824 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -63,7 +63,7 @@
 
 #elif defined(USE_MPCxxx)
 
-#define MAX_CPU     2
+#define MAX_CPU    32
 #define MAX_IRQ   128
 #define MAX_DBL     0
 #define MAX_MBX     0
@@ -507,7 +507,7 @@ static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
         break;
     case IRQ_IDE:
         tmp = val & 0xC0000000;
-        tmp |= val & ((1 << MAX_CPU) - 1);
+        tmp |= val & ((1ULL << MAX_CPU) - 1);
         opp->src[n_IRQ].ide = tmp;
         DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
         break;
@@ -1288,7 +1288,7 @@ static void mpic_reset (void *opaque)
 
     mpp->glbc = 0x80000000;
     /* Initialise controller registers */
-    mpp->frep = 0x004f0002;
+    mpp->frep = 0x004f0002 | ((MAX_CPU - 1) << 8);
     mpp->veni = VENI;
     mpp->pint = 0x00000000;
     mpp->spve = 0x0000FFFF;
@@ -1685,10 +1685,6 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
         {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
     };
 
-    /* XXX: for now, only one CPU is supported */
-    if (nb_cpus != 1)
-        return NULL;
-
     mpp = qemu_mallocz(sizeof(openpic_t));
 
     for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
-- 
1.6.0.2

[Qemu-devel] [PATCH 09/23] PPC: E500: create multiple envs

[Alexander Graf]

When creating a VM, we should go through smp_cpus and create a virtual CPU for
every CPU the user requested. This patch adds support for that and moves some
code around to make that more convenient.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_mpc8544ds.c |   44 +++++++++++++++++++++++++++++---------------
 1 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index b739ce2..cefb415 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -226,7 +226,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
                          const char *cpu_model)
 {
     PCIBus *pci_bus;
-    CPUState *env;
+    CPUState *env = NULL;
     uint64_t elf_entry;
     uint64_t elf_lowaddr;
     target_phys_addr_t entry=0;
@@ -240,24 +240,40 @@ static void mpc8544ds_init(ram_addr_t ram_size,
     qemu_irq *irqs, *mpic;
     DeviceState *dev;
     struct boot_info *boot_info;
+    CPUState *firstenv = NULL;
 
-    /* Setup CPU */
+    /* Setup CPUs */
     if (cpu_model == NULL) {
         cpu_model = "e500v2_v30";
     }
 
-    env = cpu_ppc_init(cpu_model);
-    if (!env) {
-        fprintf(stderr, "Unable to initialize CPU!\n");
-        exit(1);
-    }
+    for (i = 0; i < smp_cpus; i++) {
+        qemu_irq *input;
+        env = cpu_ppc_init(cpu_model);
+        if (!env) {
+            fprintf(stderr, "Unable to initialize CPU!\n");
+            exit(1);
+        }
+
+        if (!firstenv) {
+            firstenv = env;
+        }
 
-    /* XXX register timer? */
-    ppc_emb_timers_init(env, 400000000, PPC_INTERRUPT_DECR);
-    ppc_dcr_init(env, NULL, NULL);
+        env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
 
-    /* Register reset handler */
-    qemu_register_reset(mpc8544ds_cpu_reset, env);
+        /* XXX register timer? */
+        ppc_emb_timers_init(env, 400000000, PPC_INTERRUPT_DECR);
+        ppc_dcr_init(env, NULL, NULL);
+        /* XXX Enable DEC interrupts - probably wrong in the backend */
+        env->spr[SPR_40x_TCR] = 1 << 26;
+
+        /* Register reset handler */
+        boot_info = qemu_mallocz(sizeof(struct boot_info));
+        qemu_register_reset(mpc8544ds_cpu_reset, env);
+        env->load_info = boot_info;
+    }
+
+    env = firstenv;
 
     /* Fixup Memory size on a alignment boundary */
     ram_size &= ~(RAM_SIZES_ALIGN - 1);
@@ -336,8 +352,6 @@ static void mpc8544ds_init(ram_addr_t ram_size,
         }
     }
 
-    boot_info = qemu_mallocz(sizeof(struct boot_info));
-
     /* If we're loading a kernel directly, we must load the device tree too. */
     if (kernel_filename) {
 #ifndef CONFIG_FDT
@@ -350,10 +364,10 @@ static void mpc8544ds_init(ram_addr_t ram_size,
             exit(1);
         }
 
+        boot_info = env->load_info;
         boot_info->entry = entry;
         boot_info->dt_base = dt_base;
     }
-    env->load_info = boot_info;
 
     if (kvm_enabled()) {
         kvmppc_init();
-- 
1.6.0.2

[Qemu-devel] [PATCH 10/23] PPC: E500: Generate IRQ lines for many CPUs

[Alexander Graf]

Now that we can generate multiple envs for all our virtual CPUs, we
also need to tell the MPIC that we have multiple CPUs connected and
connect them all to the respective virtual interrupt lines.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_mpc8544ds.c |   17 ++++++++++++-----
 1 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index cefb415..7ce9bc7 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -237,7 +237,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
     target_long initrd_size=0;
     int i=0;
     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
-    qemu_irq *irqs, *mpic;
+    qemu_irq **irqs, *mpic;
     DeviceState *dev;
     struct boot_info *boot_info;
     CPUState *firstenv = NULL;
@@ -247,6 +247,8 @@ static void mpc8544ds_init(ram_addr_t ram_size,
         cpu_model = "e500v2_v30";
     }
 
+    irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
+    irqs[0] = qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
     for (i = 0; i < smp_cpus; i++) {
         qemu_irq *input;
         env = cpu_ppc_init(cpu_model);
@@ -259,6 +261,10 @@ static void mpc8544ds_init(ram_addr_t ram_size,
             firstenv = env;
         }
 
+        irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
+        input = (qemu_irq *)env->irq_inputs;
+        irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
+        irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
         env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
 
         /* XXX register timer? */
@@ -283,10 +289,11 @@ static void mpc8544ds_init(ram_addr_t ram_size,
                                  "mpc8544ds.ram", ram_size));
 
     /* MPIC */
-    irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
-    irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT];
-    irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT];
-    mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
+    mpic = mpic_init(MPC8544_MPIC_REGS_BASE, smp_cpus, irqs, NULL);
+
+    if (!mpic) {
+        cpu_abort(env, "MPIC failed to initialize\n");
+    }
 
     /* Serial */
     if (serial_hds[0]) {
-- 
1.6.0.2

[Qemu-devel] [PATCH 11/23] PPC: E500: Use spin code for secondary CPUs

[Alexander Graf]

When running with more than one CPU in -kernel mode, we need to have the
secondary CPUs spin in a special u-boot compatible loop that reads out a
so called "spin table" and checks for updates.

This patch makes sure secondary CPUs use the spin code and execute it
first thing when they execute.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_mpc8544ds.c |   17 +++++++++++++----
 1 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 7ce9bc7..0c6cdf2 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -227,6 +227,8 @@ static void mpc8544ds_init(ram_addr_t ram_size,
 {
     PCIBus *pci_bus;
     CPUState *env = NULL;
+    char *spin_filename;
+    uint64_t spin_entry;
     uint64_t elf_entry;
     uint64_t elf_lowaddr;
     target_phys_addr_t entry=0;
@@ -242,6 +244,15 @@ static void mpc8544ds_init(ram_addr_t ram_size,
     struct boot_info *boot_info;
     CPUState *firstenv = NULL;
 
+    /* Register Memory */
+    cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(NULL,
+                                 "mpc8544ds.ram", ram_size));
+
+    /* Load Spin Code */
+    spin_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "ppc_spin.elf");
+    load_elf(spin_filename, NULL, NULL, &spin_entry,
+             NULL, NULL, 1, ELF_MACHINE, 0);
+
     /* Setup CPUs */
     if (cpu_model == NULL) {
         cpu_model = "e500v2_v30";
@@ -276,6 +287,8 @@ static void mpc8544ds_init(ram_addr_t ram_size,
         /* Register reset handler */
         boot_info = qemu_mallocz(sizeof(struct boot_info));
         qemu_register_reset(mpc8544ds_cpu_reset, env);
+        boot_info->entry = spin_entry;
+        boot_info->dt_base = 0x7800000 + (i * 0x100);
         env->load_info = boot_info;
     }
 
@@ -284,10 +297,6 @@ static void mpc8544ds_init(ram_addr_t ram_size,
     /* Fixup Memory size on a alignment boundary */
     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 
-    /* Register Memory */
-    cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(NULL,
-                                 "mpc8544ds.ram", ram_size));
-
     /* MPIC */
     mpic = mpic_init(MPC8544_MPIC_REGS_BASE, smp_cpus, irqs, NULL);
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 12/23] device tree: add nop_node

[Alexander Graf]

We have a qemu internal abstraction layer on FDT. While I'm not fully convinced
we need it at all, it's missing the nop_node functionality that we now need
on e500. So let's add it and think about the general future of that API later.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 device_tree.c |   11 +++++++++++
 device_tree.h |    1 +
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/device_tree.c b/device_tree.c
index f5d5eb1..ec79dba 100644
--- a/device_tree.c
+++ b/device_tree.c
@@ -107,3 +107,14 @@ int qemu_devtree_setprop_string(void *fdt, const char *node_path,
 
     return fdt_setprop_string(fdt, offset, property, string);
 }
+
+int qemu_devtree_nop_node(void *fdt, const char *node_path)
+{
+    int offset;
+
+    offset = fdt_path_offset(fdt, node_path);
+    if (offset < 0)
+        return offset;
+
+    return fdt_nop_node(fdt, offset);
+}
diff --git a/device_tree.h b/device_tree.h
index cecd98f..76fce5f 100644
--- a/device_tree.h
+++ b/device_tree.h
@@ -22,5 +22,6 @@ int qemu_devtree_setprop_cell(void *fdt, const char *node_path,
                               const char *property, uint32_t val);
 int qemu_devtree_setprop_string(void *fdt, const char *node_path,
                                 const char *property, const char *string);
+int qemu_devtree_nop_node(void *fdt, const char *node_path);
 
 #endif /* __DEVICE_TREE_H__ */
-- 
1.6.0.2

[Qemu-devel] [PATCH 13/23] PPC: bamboo: Move host fdt copy to target

[Alexander Graf]

We have some code in generic kvm_ppc.c that is only used by 440. Move to
the 440 specific device code.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc440_bamboo.c   |   37 +++++++++++++++++++++++++++++++++++--
 target-ppc/kvm_ppc.c |   30 ------------------------------
 target-ppc/kvm_ppc.h |    1 -
 3 files changed, 35 insertions(+), 33 deletions(-)

diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
index 20b8629..a059f6b 100644
--- a/hw/ppc440_bamboo.c
+++ b/hw/ppc440_bamboo.c
@@ -31,6 +31,38 @@
 #define FDT_ADDR     0x1800000
 #define RAMDISK_ADDR 0x1900000
 
+#ifdef CONFIG_FDT
+static int bamboo_copy_host_cell(void *fdt, const char *node, const char *prop)
+{
+    uint32_t cell;
+    int ret;
+
+    ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
+    if (ret < 0) {
+        fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
+        goto out;
+    }
+
+    ret = qemu_devtree_setprop_cell(fdt, node, prop, cell);
+    if (ret < 0) {
+        fprintf(stderr, "couldn't set guest %s/%s\n", node, prop);
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+static void bamboo_fdt_update(void *fdt)
+{
+    /* Copy data from the host device tree into the guest. Since the guest can
+     * directly access the timebase without host involvement, we must expose
+     * the correct frequencies. */
+    bamboo_copy_host_cell(fdt, "/cpus/cpu@0", "clock-frequency");
+    bamboo_copy_host_cell(fdt, "/cpus/cpu@0", "timebase-frequency");
+}
+#endif
+
 static int bamboo_load_device_tree(target_phys_addr_t addr,
                                      uint32_t ramsize,
                                      target_phys_addr_t initrd_base,
@@ -76,8 +108,9 @@ static int bamboo_load_device_tree(target_phys_addr_t addr,
     if (ret < 0)
         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 
-    if (kvm_enabled())
-        kvmppc_fdt_update(fdt);
+    if (kvm_enabled()) {
+        bamboo_fdt_update(fdt);
+    }
 
     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
     qemu_free(fdt);
diff --git a/target-ppc/kvm_ppc.c b/target-ppc/kvm_ppc.c
index 536fcab..7cc522a 100644
--- a/target-ppc/kvm_ppc.c
+++ b/target-ppc/kvm_ppc.c
@@ -54,36 +54,6 @@ free:
     free(path);
     return ret;
 }
-
-static int kvmppc_copy_host_cell(void *fdt, const char *node, const char *prop)
-{
-    uint32_t cell;
-    int ret;
-
-    ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
-    if (ret < 0) {
-        fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
-        goto out;
-    }
-
-    ret = qemu_devtree_setprop_cell(fdt, node, prop, cell);
-    if (ret < 0) {
-        fprintf(stderr, "couldn't set guest %s/%s\n", node, prop);
-        goto out;
-    }
-
-out:
-    return ret;
-}
-
-void kvmppc_fdt_update(void *fdt)
-{
-    /* Copy data from the host device tree into the guest. Since the guest can
-     * directly access the timebase without host involvement, we must expose
-     * the correct frequencies. */
-    kvmppc_copy_host_cell(fdt, "/cpus/cpu@0", "clock-frequency");
-    kvmppc_copy_host_cell(fdt, "/cpus/cpu@0", "timebase-frequency");
-}
 #endif
 
 static void kvmppc_timer_hack(void *opaque)
diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index 45a1373..2f32249 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -10,7 +10,6 @@
 #define __KVM_PPC_H__
 
 void kvmppc_init(void);
-void kvmppc_fdt_update(void *fdt);
 #ifndef CONFIG_KVM
 static inline int kvmppc_read_host_property(const char *node_path, const char *prop,
                                             void *val, size_t len)
-- 
1.6.0.2

[Qemu-devel] [PATCH 14/23] PPC: KVM: Add generic function to read host clockfreq

[Alexander Graf]

We need to find out the host's clock-frequency when running on KVM, so
let's export a respective function.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/kvm.c     |   65 ++++++++++++++++++++++++++++++++++++++++++++++++++
 target-ppc/kvm_ppc.h |    1 +
 2 files changed, 66 insertions(+), 0 deletions(-)

diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 21f35af..13aa9ae 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -14,6 +14,7 @@
  *
  */
 
+#include <dirent.h>
 #include <sys/types.h>
 #include <sys/ioctl.h>
 #include <sys/mman.h>
@@ -38,6 +39,8 @@
     do { } while (0)
 #endif
 
+#define PROC_DEVTREE_CPU      "/proc/device-tree/cpus/"
+
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
     KVM_CAP_LAST_INFO
 };
@@ -509,6 +512,68 @@ uint32_t kvmppc_get_tbfreq(void)
     return retval;
 }
 
+/* Try to find a device tree node for a CPU with clock-frequency property */
+static int kvmppc_find_cpu_dt(char *buf, int buf_len)
+{
+    struct dirent *dirp;
+    DIR *dp;
+
+    if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) {
+        printf("Can't open directory " PROC_DEVTREE_CPU "\n");
+        return -1;
+    }
+
+    buf[0] = '\0';
+    while ((dirp = readdir(dp)) != NULL) {
+        FILE *f;
+        snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
+                 dirp->d_name);
+        f = fopen(buf, "r");
+        if (f) {
+            snprintf(buf, buf_len, "%scpus/%s", PROC_DEVTREE_CPU, dirp->d_name);
+            fclose(f);
+            break;
+        }
+        buf[0] = '\0';
+    }
+    closedir(dp);
+    if (buf[0] == '\0') {
+        printf("Unknown host!\n");
+        return -1;
+    }
+
+    return 0;
+}
+
+uint32_t kvmppc_get_clockfreq(void)
+{
+    char buf[512];
+    uint32_t tb;
+    FILE *f;
+    int len;
+
+    if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
+        return 0;
+    }
+
+    snprintf(buf, sizeof(buf), "%s/clock-frequency", buf);
+
+    f = fopen(buf, "rb");
+    if (!f) {
+        return -1;
+    }
+
+    len = fread(&tb, sizeof(tb), 1, f);
+    if (len != 1) {
+        goto err;
+    }
+
+    return tb;
+err:
+    fclose(f);
+    return 0;
+}
+
 int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len)
 {
     uint32_t *hc = (uint32_t*)buf;
diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index 2f32249..1827a13 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -23,6 +23,7 @@ int kvmppc_read_host_property(const char *node_path, const char *prop,
 #endif
 
 uint32_t kvmppc_get_tbfreq(void);
+uint32_t kvmppc_get_clockfreq(void);
 int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len);
 int kvmppc_set_interrupt(CPUState *env, int irq, int level);
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 15/23] PPC: E500: Use generic kvm function for freq

[Alexander Graf]

Now that we have generic KVM functions to read out the host tb and clock
frequencies, let's use them in the e500 code!

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_mpc8544ds.c |   44 +++++++++-----------------------------------
 1 files changed, 9 insertions(+), 35 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 0c6cdf2..c174ae8 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -14,8 +14,6 @@
  * (at your option) any later version.
  */
 
-#include <dirent.h>
-
 #include "config.h"
 #include "qemu-common.h"
 #include "net.h"
@@ -96,6 +94,9 @@ static int mpc8544_load_device_tree(CPUState *env,
     int fdt_size;
     void *fdt;
     uint8_t hypercall[16];
+    char cpu_name[128] = "/cpus/PowerPC,8544@0";
+    uint32_t clock_freq = 400000000;
+    uint32_t tb_freq = 400000000;
 
     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
     if (!filename) {
@@ -133,32 +134,9 @@ static int mpc8544_load_device_tree(CPUState *env,
         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 
     if (kvm_enabled()) {
-        struct dirent *dirp;
-        DIR *dp;
-        char buf[128];
-
-        if ((dp = opendir("/proc/device-tree/cpus/")) == NULL) {
-            printf("Can't open directory /proc/device-tree/cpus/\n");
-            ret = -1;
-            goto out;
-        }
-
-        buf[0] = '\0';
-        while ((dirp = readdir(dp)) != NULL) {
-            if (strncmp(dirp->d_name, "PowerPC", 7) == 0) {
-                snprintf(buf, 128, "/cpus/%s", dirp->d_name);
-                break;
-            }
-        }
-        closedir(dp);
-        if (buf[0] == '\0') {
-            printf("Unknow host!\n");
-            ret = -1;
-            goto out;
-        }
-
-        mpc8544_copy_soc_cell(fdt, buf, "clock-frequency");
-        mpc8544_copy_soc_cell(fdt, buf, "timebase-frequency");
+        /* Read out host's frequencies */
+        clock_freq = kvmppc_get_clockfreq();
+        tb_freq = kvmppc_get_tbfreq();
 
         /* indicate KVM hypercall interface */
         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
@@ -166,15 +144,11 @@ static int mpc8544_load_device_tree(CPUState *env,
         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
                              hypercall, sizeof(hypercall));
-    } else {
-        const uint32_t freq = 400000000;
-
-        qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
-                                  "clock-frequency", freq);
-        qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
-                                  "timebase-frequency", freq);
     }
 
+    qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
+    qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
+
     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
     qemu_free(fdt);
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 16/23] PPC: E500: Remove mpc8544_copy_soc_cell

[Alexander Graf]

We don't need mpc8544_copy_soc_cell anymore, since we're explicitly reading
host values and writing guest values respectively.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_mpc8544ds.c |   24 ------------------------
 1 files changed, 0 insertions(+), 24 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index c174ae8..0509193 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -56,30 +56,6 @@ struct boot_info
     uint32_t entry;
 };
 
-#ifdef CONFIG_FDT
-static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop)
-{
-    uint32_t cell;
-    int ret;
-
-    ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
-    if (ret < 0) {
-        fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
-        goto out;
-    }
-
-    ret = qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
-                                prop, cell);
-    if (ret < 0) {
-        fprintf(stderr, "couldn't set guest /cpus/PowerPC,8544@0/%s\n", prop);
-        goto out;
-    }
-
-out:
-    return ret;
-}
-#endif
-
 static int mpc8544_load_device_tree(CPUState *env,
                                     target_phys_addr_t addr,
                                     uint32_t ramsize,
-- 
1.6.0.2

[Qemu-devel] [PATCH 17/23] PPC: bamboo: Use kvm api for freq and clock frequencies

[Alexander Graf]

Now that we have nice and shiny APIs to read out the host's clock and timebase
frequencies, let's use them in the bamboo code as well!

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc440_bamboo.c |   45 ++++++++++++---------------------------------
 1 files changed, 12 insertions(+), 33 deletions(-)

diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
index a059f6b..afcf97b 100644
--- a/hw/ppc440_bamboo.c
+++ b/hw/ppc440_bamboo.c
@@ -31,38 +31,6 @@
 #define FDT_ADDR     0x1800000
 #define RAMDISK_ADDR 0x1900000
 
-#ifdef CONFIG_FDT
-static int bamboo_copy_host_cell(void *fdt, const char *node, const char *prop)
-{
-    uint32_t cell;
-    int ret;
-
-    ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
-    if (ret < 0) {
-        fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
-        goto out;
-    }
-
-    ret = qemu_devtree_setprop_cell(fdt, node, prop, cell);
-    if (ret < 0) {
-        fprintf(stderr, "couldn't set guest %s/%s\n", node, prop);
-        goto out;
-    }
-
-out:
-    return ret;
-}
-
-static void bamboo_fdt_update(void *fdt)
-{
-    /* Copy data from the host device tree into the guest. Since the guest can
-     * directly access the timebase without host involvement, we must expose
-     * the correct frequencies. */
-    bamboo_copy_host_cell(fdt, "/cpus/cpu@0", "clock-frequency");
-    bamboo_copy_host_cell(fdt, "/cpus/cpu@0", "timebase-frequency");
-}
-#endif
-
 static int bamboo_load_device_tree(target_phys_addr_t addr,
                                      uint32_t ramsize,
                                      target_phys_addr_t initrd_base,
@@ -75,6 +43,8 @@ static int bamboo_load_device_tree(target_phys_addr_t addr,
     char *filename;
     int fdt_size;
     void *fdt;
+    uint32_t tb_freq = 400000000;
+    uint32_t clock_freq = 400000000;
 
     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
     if (!filename) {
@@ -108,10 +78,19 @@ static int bamboo_load_device_tree(target_phys_addr_t addr,
     if (ret < 0)
         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 
+    /* Copy data from the host device tree into the guest. Since the guest can
+     * directly access the timebase without host involvement, we must expose
+     * the correct frequencies. */
     if (kvm_enabled()) {
-        bamboo_fdt_update(fdt);
+        tb_freq = kvmppc_get_tbfreq();
+        clock_freq = kvmppc_get_clockfreq();
     }
 
+    qemu_devtree_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
+                              clock_freq);
+    qemu_devtree_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
+                              tb_freq);
+
     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
     qemu_free(fdt);
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 18/23] PPC: KVM: Remove kvmppc_read_host_property

[Alexander Graf]

We just got rid of the last user of kvmppc_read_host_property, so we
can now safely remove it.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/kvm_ppc.c |   35 -----------------------------------
 target-ppc/kvm_ppc.h |   11 -----------
 2 files changed, 0 insertions(+), 46 deletions(-)

diff --git a/target-ppc/kvm_ppc.c b/target-ppc/kvm_ppc.c
index 7cc522a..0c9b530 100644
--- a/target-ppc/kvm_ppc.c
+++ b/target-ppc/kvm_ppc.c
@@ -21,41 +21,6 @@
 static QEMUTimer *kvmppc_timer;
 static unsigned int kvmppc_timer_rate;
 
-#ifdef CONFIG_FDT
-int kvmppc_read_host_property(const char *node_path, const char *prop,
-                                     void *val, size_t len)
-{
-    char *path;
-    FILE *f;
-    int ret = 0;
-    int pathlen;
-
-    pathlen = snprintf(NULL, 0, "%s/%s/%s", PROC_DEVTREE_PATH, node_path, prop)
-              + 1;
-    path = qemu_malloc(pathlen);
-
-    snprintf(path, pathlen, "%s/%s/%s", PROC_DEVTREE_PATH, node_path, prop);
-
-    f = fopen(path, "rb");
-    if (f == NULL) {
-        ret = errno;
-        goto free;
-    }
-
-    len = fread(val, len, 1, f);
-    if (len != 1) {
-        ret = ferror(f);
-        goto close;
-    }
-
-close:
-    fclose(f);
-free:
-    free(path);
-    return ret;
-}
-#endif
-
 static void kvmppc_timer_hack(void *opaque)
 {
     qemu_service_io();
diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index 1827a13..523825d 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -10,17 +10,6 @@
 #define __KVM_PPC_H__
 
 void kvmppc_init(void);
-#ifndef CONFIG_KVM
-static inline int kvmppc_read_host_property(const char *node_path, const char *prop,
-                                            void *val, size_t len)
-{
-    assert(0);
-    return -ENOSYS;
-}
-#else
-int kvmppc_read_host_property(const char *node_path, const char *prop,
-                                     void *val, size_t len);
-#endif
 
 uint32_t kvmppc_get_tbfreq(void);
 uint32_t kvmppc_get_clockfreq(void);
-- 
1.6.0.2

[Qemu-devel] [PATCH 19/23] PPC: KVM: Add stubs for kvm helper functions

[Alexander Graf]

We have a bunch of helper functions that don't have any stubs for them in case
we don't have CONFIG_KVM enabled. That didn't bite us so far, because gcc can
optimize them out pretty well, but we should really provide them.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/kvm_ppc.h |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index 523825d..df5730d 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -11,11 +11,37 @@
 
 void kvmppc_init(void);
 
+#ifdef CONFIG_KVM
+
 uint32_t kvmppc_get_tbfreq(void);
 uint32_t kvmppc_get_clockfreq(void);
 int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len);
 int kvmppc_set_interrupt(CPUState *env, int irq, int level);
 
+#else
+
+static inline uint32_t kvmppc_get_tbfreq(void)
+{
+    return 0;
+}
+
+static inline uint32_t kvmppc_get_clockfreq(void)
+{
+    return 0;
+}
+
+static inline int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len)
+{
+    return -1;
+}
+
+static inline int kvmppc_set_interrupt(CPUState *env, int irq, int level)
+{
+    return -1;
+}
+
+#endif
+
 #ifndef CONFIG_KVM
 #define kvmppc_eieio() do { } while (0)
 #else
-- 
1.6.0.2

[Qemu-devel] [PATCH 20/23] PPC: E500: Update freqs for all CPUs

[Alexander Graf]

Now that we can so nicely find out the host's frequencies, we should also
make sure that we get them into all virtual CPUs' device tree nodes.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_mpc8544ds.c |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 0509193..85d8da1 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -70,9 +70,9 @@ static int mpc8544_load_device_tree(CPUState *env,
     int fdt_size;
     void *fdt;
     uint8_t hypercall[16];
-    char cpu_name[128] = "/cpus/PowerPC,8544@0";
     uint32_t clock_freq = 400000000;
     uint32_t tb_freq = 400000000;
+    int i;
 
     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
     if (!filename) {
@@ -122,8 +122,12 @@ static int mpc8544_load_device_tree(CPUState *env,
                              hypercall, sizeof(hypercall));
     }
 
-    qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
-    qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
+    for (i = 0; i < smp_cpus; i++) {
+        char cpu_name[128];
+        snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", i);
+        qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
+        qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
+    }
 
     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
     qemu_free(fdt);
-- 
1.6.0.2

[Qemu-devel] [PATCH 21/23] PPC: E500: Remove unneeded CPU nodes

[Alexander Graf]

We should only keep CPU nodes in the device tree around that we really have
virtual CPUs for. So remove all superfluous entries that we just keep there
in case someone wants to create a lot of vCPUs.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_mpc8544ds.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 85d8da1..cccf79b 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -129,6 +129,12 @@ static int mpc8544_load_device_tree(CPUState *env,
         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
     }
 
+    for (i = smp_cpus; i < 32; i++) {
+        char cpu_name[128];
+        snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", i);
+        qemu_devtree_nop_node(fdt, cpu_name);
+    }
+
     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
     qemu_free(fdt);
 
-- 
1.6.0.2

[Qemu-devel] [PATCH 22/23] PPC: E500: Update cpu-release-addr property in cpu nodes

[Alexander Graf]

The guest OS wants to know where the guest spins, so let's tell him while
updating the CPU nodes with the frequencies anyways.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_mpc8544ds.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index cccf79b..d22ee37 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -124,9 +124,13 @@ static int mpc8544_load_device_tree(CPUState *env,
 
     for (i = 0; i < smp_cpus; i++) {
         char cpu_name[128];
+        uint64_t cpu_release_addr[] = { cpu_to_be64(0x7800000 + (i * 0x100)) };
+
         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", i);
         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
+        qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr",
+                             cpu_release_addr, sizeof(cpu_release_addr));
     }
 
     for (i = smp_cpus; i < 32; i++) {
-- 
1.6.0.2

[Qemu-devel] [PATCH 23/23] PPC: E500: Bump CPU count to 32

[Alexander Graf]

Now that we have everything in place, make the machine description
aware of the fact that we can now handle 32 virtual CPUs!

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_mpc8544ds.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index d22ee37..ddcaffd 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -358,6 +358,7 @@ static QEMUMachine mpc8544ds_machine = {
     .name = "mpc8544ds",
     .desc = "mpc8544ds",
     .init = mpc8544ds_init,
+    .max_cpus = 32,
 };
 
 static void mpc8544ds_machine_init(void)
-- 
1.6.0.2

Re: [Qemu-devel] [PATCH 01/23] PPC: Add secondary CPU spinning code

[Scott Wood]

On Thu, 21 Jul 2011 03:27:12 +0200
Alexander Graf <agraf@suse.de> wrote:

> When directly starting an SMP system with -kernel on PPC e500, we need to
> simulate the spin table code from u-boot. This code adds a small c file
> plus generated .elf file that enable secondary CPUs to spin just like they
> would with u-boot.

Why not just handle the spin table as an MMIO region?

Besides being simpler, it avoids any spinning overhead if the guest doesn't
spin up all the cpus.

> diff --git a/pc-bios/ppc_spin.c b/pc-bios/ppc_spin.c
> new file mode 100644
> index 0000000..e46a6a7
> --- /dev/null
> +++ b/pc-bios/ppc_spin.c
> @@ -0,0 +1,97 @@
> +#include <stdio.h>
> +#include <stdint.h>
> +
> +/*
> + * Secondary CPU spin code
> + *
> + * Compile using: gcc -m32 -nostdlib ppc_spin.c -o ppc_spin.elf -Os \
> + *                    -fno-stack-protector -Wl,-Ttext,0x7700000
> + */
> +
> +/* Initialize stack pointer */
> +asm (
> +"    .global _start             \n"
> +"    _start:                    \n"
> +"    addis   1, 3, 0x10000@h    \n"
> +"    b       spin               \n");
> +
> +typedef struct spin_info {
> +    uint32_t addr_hi;
> +    uint32_t addr;
> +    uint32_t r3_hi;
> +    uint32_t r3;
> +    uint32_t resv;
> +    uint32_t pir;
> +    uint32_t r6_hi;
> +    uint32_t r6;
> +} SpinInfo;
> +
> +#define __stringify_1(x...)     #x
> +#define __stringify(x...)       __stringify_1(x)
> +
> +#define mfspr(rn)       ({unsigned long rval; \
> +                        asm volatile("mfspr %0," __stringify(rn) \
> +                                : "=r" (rval)); rval;})
> +#define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)\
> +                                     : "memory")
> +static inline void mtdec(unsigned long v)
> +{
> +    asm volatile("mtdec %0" : : "r" (v));
> +}
> +
> +static inline void mtmsr(unsigned long msr)
> +{
> +    asm("mtmsr %0" : : "r"(msr));
> +}
> +
> +#define __MASK(X)        (1UL<<(X))
> +#define MSR_WE_LG        18              /* Wait State Enable */
> +#define MSR_EE_LG        15              /* External Interrupt Enable */
> +#define MSR_WE           __MASK(MSR_WE_LG)       /* Wait State Enable */
> +#define MSR_EE           __MASK(MSR_EE_LG)       /* External Interrupt Enable */
> +#define SPR_PIR          0x11E
> +#define SPR_HID0         (0x3F0)
> +#define SPR_BOOKE_IVOR10 (0x19A)
> +#define SPR_BOOKE_IVPR   (0x03F)
> +
> +void loop(void);
> +
> +__attribute__((noreturn)) void spin(unsigned long ptr)
> +{
> +    volatile SpinInfo *info = (void*)ptr;
> +    uint32_t pir = mfspr(SPR_PIR);
> +    __attribute__((noreturn)) void (*entry)(
> +        unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6,
> +        unsigned long r7, unsigned long r8, unsigned long r9);
> +    unsigned long dec_p = (unsigned long)loop;
> +
> +    info->pir = pir;
> +    info->r3 = pir;
> +    info->addr = 1;
> +    info->r6 = 0;
> +
> +    /* we don't want to keep the other CPUs from running, so set the IVOR for
> +       DEC to our loop and only check for info->addr every other cycle */
> +
> +    mtspr(SPR_HID0, 0x00E00000);
> +    mtspr(SPR_BOOKE_IVOR10, dec_p & 0xfff);
> +    mtspr(SPR_BOOKE_IVPR, dec_p & ~0xfff);
> +loop:
> +    asm volatile (".global loop\n"
> +        "   loop:" : : : "memory", "cc");

You're jumping through a lot of hoops to (nominally) do this in C.

> +    info->pir = pir;

While I'm fine with not allowing the guest to set PIR (the ISA says it's
read-only in virtualized implementations), I'm not sure we should be
overwriting the spintable value here.

> +    entry = (void*)(unsigned long)info->addr;

You're ignoring addr_hi, and you should create an IMA appropriate for the
guest's chosen entry point rather than assume it's in the first 64M.

And don't forget about r3_hi and r6_hi on future 64-bit targets.

The function pointer approach might also run into trouble on 64-bit, due
to ABI weirdness.

> diff --git a/pc-bios/ppc_spin.elf b/pc-bios/ppc_spin.elf
> new file mode 100755
> index 0000000000000000000000000000000000000000..71c872b2d4685100b0050d549735662d7d763e08
> GIT binary patch
> literal 66553

Must this go into the tree as a binary?  Why can't it be built when qemu is
built (if it's needed at all)?

This has proven to be rather annoying with the dtb as well.

-Scott

Re: [Qemu-devel] [PATCH 03/23] PPC: Add CPU definitions for up to 32 guest CPUs

[Scott Wood]

On Thu, 21 Jul 2011 03:27:14 +0200
Alexander Graf <agraf@suse.de> wrote:

> All guest CPUs need to be specified in the device trees. Since removing nodes
> is easy with FDT, but adding nodes is not, we just put 32 CPU nodes into the
> device tree and remove them later on init when not used.

Adding nodes isn't that hard...

I'm also hesitant to stick so many CPUs on something modeled after an
e500v2-era mpc85xx.  E.g. in the MPIC the upper bits of xIDR are used
for EP/CIx.  The newer MPIC used in p4080 and such move crit/mcheck routing
into a separate register.  There are similar constraints in guts (power
management), and possibly elsewhere.

-Scott

Re: [Qemu-devel] [PATCH 07/23] PPC: Remove cINT code from MPIC

[Scott Wood]

On Thu, 21 Jul 2011 03:27:18 +0200
Alexander Graf <agraf@suse.de> wrote:

> The current code treats some bits in IDE as special for critical interrupts.
> While there is logic to route interrupts as critical, that happens through
> a different register. So for now I'm just removing the check to enable up to 32
> virtual CPUs.

This depends on the MPIC version.  The behavior should match what we
advertise to the guest.

-Scott

Re: [Qemu-devel] [PATCH 01/23] PPC: Add secondary CPU spinning code

[Alexander Graf]

On 21.07.2011, at 18:38, Scott Wood wrote:

> On Thu, 21 Jul 2011 03:27:12 +0200
> Alexander Graf <agraf@suse.de> wrote:
> 
>> When directly starting an SMP system with -kernel on PPC e500, we need to
>> simulate the spin table code from u-boot. This code adds a small c file
>> plus generated .elf file that enable secondary CPUs to spin just like they
>> would with u-boot.
> 
> Why not just handle the spin table as an MMIO region?
> 
> Besides being simpler, it avoids any spinning overhead if the guest doesn't
> spin up all the cpus.

Hmm - sounds like a nice idea. We'd have to reserve the region in the dt, but overall I agree that it might end up being simpler.

> 
>> diff --git a/pc-bios/ppc_spin.c b/pc-bios/ppc_spin.c
>> new file mode 100644
>> index 0000000..e46a6a7
>> --- /dev/null
>> +++ b/pc-bios/ppc_spin.c
>> @@ -0,0 +1,97 @@
>> +#include <stdio.h>
>> +#include <stdint.h>
>> +
>> +/*
>> + * Secondary CPU spin code
>> + *
>> + * Compile using: gcc -m32 -nostdlib ppc_spin.c -o ppc_spin.elf -Os \
>> + *                    -fno-stack-protector -Wl,-Ttext,0x7700000
>> + */
>> +
>> +/* Initialize stack pointer */
>> +asm (
>> +"    .global _start             \n"
>> +"    _start:                    \n"
>> +"    addis   1, 3, 0x10000@h    \n"
>> +"    b       spin               \n");
>> +
>> +typedef struct spin_info {
>> +    uint32_t addr_hi;
>> +    uint32_t addr;
>> +    uint32_t r3_hi;
>> +    uint32_t r3;
>> +    uint32_t resv;
>> +    uint32_t pir;
>> +    uint32_t r6_hi;
>> +    uint32_t r6;
>> +} SpinInfo;
>> +
>> +#define __stringify_1(x...)     #x
>> +#define __stringify(x...)       __stringify_1(x)
>> +
>> +#define mfspr(rn)       ({unsigned long rval; \
>> +                        asm volatile("mfspr %0," __stringify(rn) \
>> +                                : "=r" (rval)); rval;})
>> +#define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)\
>> +                                     : "memory")
>> +static inline void mtdec(unsigned long v)
>> +{
>> +    asm volatile("mtdec %0" : : "r" (v));
>> +}
>> +
>> +static inline void mtmsr(unsigned long msr)
>> +{
>> +    asm("mtmsr %0" : : "r"(msr));
>> +}
>> +
>> +#define __MASK(X)        (1UL<<(X))
>> +#define MSR_WE_LG        18              /* Wait State Enable */
>> +#define MSR_EE_LG        15              /* External Interrupt Enable */
>> +#define MSR_WE           __MASK(MSR_WE_LG)       /* Wait State Enable */
>> +#define MSR_EE           __MASK(MSR_EE_LG)       /* External Interrupt Enable */
>> +#define SPR_PIR          0x11E
>> +#define SPR_HID0         (0x3F0)
>> +#define SPR_BOOKE_IVOR10 (0x19A)
>> +#define SPR_BOOKE_IVPR   (0x03F)
>> +
>> +void loop(void);
>> +
>> +__attribute__((noreturn)) void spin(unsigned long ptr)
>> +{
>> +    volatile SpinInfo *info = (void*)ptr;
>> +    uint32_t pir = mfspr(SPR_PIR);
>> +    __attribute__((noreturn)) void (*entry)(
>> +        unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6,
>> +        unsigned long r7, unsigned long r8, unsigned long r9);
>> +    unsigned long dec_p = (unsigned long)loop;
>> +
>> +    info->pir = pir;
>> +    info->r3 = pir;
>> +    info->addr = 1;
>> +    info->r6 = 0;
>> +
>> +    /* we don't want to keep the other CPUs from running, so set the IVOR for
>> +       DEC to our loop and only check for info->addr every other cycle */
>> +
>> +    mtspr(SPR_HID0, 0x00E00000);
>> +    mtspr(SPR_BOOKE_IVOR10, dec_p & 0xfff);
>> +    mtspr(SPR_BOOKE_IVPR, dec_p & ~0xfff);
>> +loop:
>> +    asm volatile (".global loop\n"
>> +        "   loop:" : : : "memory", "cc");
> 
> You're jumping through a lot of hoops to (nominally) do this in C.

Yeah, but at the end of the day C is a lot more readable than asm IMHO :).

> 
>> +    info->pir = pir;
> 
> While I'm fine with not allowing the guest to set PIR (the ISA says it's
> read-only in virtualized implementations), I'm not sure we should be
> overwriting the spintable value here.

I merely do what the u-boot code is doing.

> 
>> +    entry = (void*)(unsigned long)info->addr;
> 
> You're ignoring addr_hi, and you should create an IMA appropriate for the
> guest's chosen entry point rather than assume it's in the first 64M.

Hm - we have a linear map of 256MB. But yes, maybe creating a mapping instead of just assuming it'll be within there is a good idea :).

> 
> And don't forget about r3_hi and r6_hi on future 64-bit targets.

The code as is is 100% 32-bit.

> 
> The function pointer approach might also run into trouble on 64-bit, due
> to ABI weirdness.
> 
>> diff --git a/pc-bios/ppc_spin.elf b/pc-bios/ppc_spin.elf
>> new file mode 100755
>> index 0000000000000000000000000000000000000000..71c872b2d4685100b0050d549735662d7d763e08
>> GIT binary patch
>> literal 66553
> 
> Must this go into the tree as a binary?  Why can't it be built when qemu is
> built (if it's needed at all)?
> 
> This has proven to be rather annoying with the dtb as well.

Yes, it does. We can't assume everyone to be running on ppc hosts or have ppc cross-compilers available. Firmware blobs have to be kept in the tree precompiled.


Alex

Re: [Qemu-devel] [PATCH 07/23] PPC: Remove cINT code from MPIC

[Alexander Graf]

On 21.07.2011, at 18:49, Scott Wood wrote:

> On Thu, 21 Jul 2011 03:27:18 +0200
> Alexander Graf <agraf@suse.de> wrote:
> 
>> The current code treats some bits in IDE as special for critical interrupts.
>> While there is logic to route interrupts as critical, that happens through
>> a different register. So for now I'm just removing the check to enable up to 32
>> virtual CPUs.
> 
> This depends on the MPIC version.  The behavior should match what we
> advertise to the guest.

Ah, good to know! That's why I couldn't find it in the spec I was looking at :). So we should clearly limit the number of CPUs then to whatever fits into that field.


Alex

Re: [Qemu-devel] [PATCH 03/23] PPC: Add CPU definitions for up to 32 guest CPUs

[Alexander Graf]

On 21.07.2011, at 18:46, Scott Wood wrote:

> On Thu, 21 Jul 2011 03:27:14 +0200
> Alexander Graf <agraf@suse.de> wrote:
> 
>> All guest CPUs need to be specified in the device trees. Since removing nodes
>> is easy with FDT, but adding nodes is not, we just put 32 CPU nodes into the
>> device tree and remove them later on init when not used.
> 
> Adding nodes isn't that hard...

Hm. I'll check again and see if I can add a node. If so, we can just completely replace the CPU definitions by self-generated ones.

> I'm also hesitant to stick so many CPUs on something modeled after an
> e500v2-era mpc85xx.  E.g. in the MPIC the upper bits of xIDR are used
> for EP/CIx.  The newer MPIC used in p4080 and such move crit/mcheck routing
> into a separate register.  There are similar constraints in guts (power
> management), and possibly elsewhere.

Good point. See my other mail. I'll fix the CI thing and limit the # of CPUs.


Alex

Re: [Qemu-devel] [PATCH 01/23] PPC: Add secondary CPU spinning code

[Scott Wood]

On Thu, 21 Jul 2011 18:49:44 +0200
Alexander Graf <agraf@suse.de> wrote:

> 
> On 21.07.2011, at 18:38, Scott Wood wrote:
> 
> > On Thu, 21 Jul 2011 03:27:12 +0200
> > Alexander Graf <agraf@suse.de> wrote:
> > 
> >> When directly starting an SMP system with -kernel on PPC e500, we need to
> >> simulate the spin table code from u-boot. This code adds a small c file
> >> plus generated .elf file that enable secondary CPUs to spin just like they
> >> would with u-boot.
> > 
> > Why not just handle the spin table as an MMIO region?
> > 
> > Besides being simpler, it avoids any spinning overhead if the guest doesn't
> > spin up all the cpus.
> 
> Hmm - sounds like a nice idea. We'd have to reserve the region in the dt, but overall I agree that it might end up being simpler.

The region needs to be reserved in the dt regardless.

> > You're jumping through a lot of hoops to (nominally) do this in C.
> 
> Yeah, but at the end of the day C is a lot more readable than asm IMHO :).

I'm not so sure in this case.

> >> +    info->pir = pir;
> > 
> > While I'm fine with not allowing the guest to set PIR (the ISA says it's
> > read-only in virtualized implementations), I'm not sure we should be
> > overwriting the spintable value here.
> 
> I merely do what the u-boot code is doing.

Never mind, ePAPR does say to update the spin table with the actual PIR
prior to entry.

> >> +    entry = (void*)(unsigned long)info->addr;
> > 
> > You're ignoring addr_hi, and you should create an IMA appropriate for the
> > guest's chosen entry point rather than assume it's in the first 64M.
> 
> Hm - we have a linear map of 256MB. But yes, maybe creating a mapping instead of just assuming it'll be within there is a good idea :).

In the KVM direct-mapped memory case there might not be any memory at all
in the first 256M.  We've got a patch in our queue to choose an appropriate
IMA at runtime.

> > And don't forget about r3_hi and r6_hi on future 64-bit targets.
> 
> The code as is is 100% 32-bit.

Right, but it'd be nice to minimize the things that silently break on
64-bit.

-Scott

Re: [Qemu-devel] [PATCH 14/23] PPC: KVM: Add generic function to read host clockfreq

[Scott Wood]

On Thu, 21 Jul 2011 03:27:25 +0200
Alexander Graf <agraf@suse.de> wrote:

> +/* Try to find a device tree node for a CPU with clock-frequency property */
> +static int kvmppc_find_cpu_dt(char *buf, int buf_len)
> +{
> +    struct dirent *dirp;
> +    DIR *dp;
> +
> +    if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) {
> +        printf("Can't open directory " PROC_DEVTREE_CPU "\n");
> +        return -1;
> +    }
> +
> +    buf[0] = '\0';
> +    while ((dirp = readdir(dp)) != NULL) {
> +        FILE *f;
> +        snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
> +                 dirp->d_name);
> +        f = fopen(buf, "r");
> +        if (f) {
> +            snprintf(buf, buf_len, "%scpus/%s", PROC_DEVTREE_CPU, dirp->d_name);
> +            fclose(f);
> +            break;
> +        }
> +        buf[0] = '\0';
> +    }
> +    closedir(dp);
> +    if (buf[0] == '\0') {
> +        printf("Unknown host!\n");
> +        return -1;
> +    }

"Unknown host!" is a little vague for an error message.

> +uint32_t kvmppc_get_clockfreq(void)
> +{
> +    char buf[512];
> +    uint32_t tb;
> +    FILE *f;
> +    int len;
> +
> +    if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
> +        return 0;
> +    }
> +
> +    snprintf(buf, sizeof(buf), "%s/clock-frequency", buf);
> +
> +    f = fopen(buf, "rb");
> +    if (!f) {
> +        return -1;
> +    }
> +
> +    len = fread(&tb, sizeof(tb), 1, f);
> +    if (len != 1) {
> +        goto err;
> +    }
> +
> +    return tb;
> +err:
> +    fclose(f);
> +    return 0;
> +}

Need to convert endian from big to host.  Also, the frequency can be 64-bit.

-Scott

Re: [Qemu-devel] [PATCH 14/23] PPC: KVM: Add generic function to read host clockfreq

[Alexander Graf]

Am 21.07.2011 um 19:51 schrieb Scott Wood <scottwood@freescale.com>:

> On Thu, 21 Jul 2011 03:27:25 +0200
> Alexander Graf <agraf@suse.de> wrote:
> 
>> +/* Try to find a device tree node for a CPU with clock-frequency property */
>> +static int kvmppc_find_cpu_dt(char *buf, int buf_len)
>> +{
>> +    struct dirent *dirp;
>> +    DIR *dp;
>> +
>> +    if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) {
>> +        printf("Can't open directory " PROC_DEVTREE_CPU "\n");
>> +        return -1;
>> +    }
>> +
>> +    buf[0] = '\0';
>> +    while ((dirp = readdir(dp)) != NULL) {
>> +        FILE *f;
>> +        snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
>> +                 dirp->d_name);
>> +        f = fopen(buf, "r");
>> +        if (f) {
>> +            snprintf(buf, buf_len, "%scpus/%s", PROC_DEVTREE_CPU, dirp->d_name);
>> +            fclose(f);
>> +            break;
>> +        }
>> +        buf[0] = '\0';
>> +    }
>> +    closedir(dp);
>> +    if (buf[0] == '\0') {
>> +        printf("Unknown host!\n");
>> +        return -1;
>> +    }
> 
> "Unknown host!" is a little vague for an error message.
> 
>> +uint32_t kvmppc_get_clockfreq(void)
>> +{
>> +    char buf[512];
>> +    uint32_t tb;
>> +    FILE *f;
>> +    int len;
>> +
>> +    if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
>> +        return 0;
>> +    }
>> +
>> +    snprintf(buf, sizeof(buf), "%s/clock-frequency", buf);
>> +
>> +    f = fopen(buf, "rb");
>> +    if (!f) {
>> +        return -1;
>> +    }
>> +
>> +    len = fread(&tb, sizeof(tb), 1, f);
>> +    if (len != 1) {
>> +        goto err;
>> +    }
>> +
>> +    return tb;
>> +err:
>> +    fclose(f);
>> +    return 0;
>> +}
> 
> Need to convert endian from big to host.  

Hm. This is kvm specific code for ppc, so only ever runs on host==big :)

> Also, the frequency can be 64-bit.

Would the parameter just be 2 cells then? Got an example how this works?

Alex

> 
> -Scott
> 

Re: [Qemu-devel] [PATCH 14/23] PPC: KVM: Add generic function to read host clockfreq

[Scott Wood]

On Thu, 21 Jul 2011 20:59:40 +0200
Alexander Graf <agraf@suse.de> wrote:

> >> +uint32_t kvmppc_get_clockfreq(void)
> >> +{
> >> +    char buf[512];
> >> +    uint32_t tb;
> >> +    FILE *f;
> >> +    int len;
> >> +
> >> +    if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
> >> +        return 0;
> >> +    }
> >> +
> >> +    snprintf(buf, sizeof(buf), "%s/clock-frequency", buf);
> >> +
> >> +    f = fopen(buf, "rb");
> >> +    if (!f) {
> >> +        return -1;
> >> +    }
> >> +
> >> +    len = fread(&tb, sizeof(tb), 1, f);
> >> +    if (len != 1) {
> >> +        goto err;
> >> +    }
> >> +
> >> +    return tb;
> >> +err:
> >> +    fclose(f);
> >> +    return 0;
> >> +}
> > 
> > Need to convert endian from big to host.  
> 
> Hm. This is kvm specific code for ppc, so only ever runs on host==big :)

Sigh.  I looked at what file it was specifically to check whether it was
in a ppc or generic file, and somehow I still didn't see the "ppc". :-P

> > Also, the frequency can be 64-bit.
> 
> Would the parameter just be 2 cells then? Got an example how this works?

Yes, it would be 2 cells.  Just check the property length.

-Scott

Re: [Qemu-devel] [PATCH 06/23] PPC: Fix IPI support in MPIC

[Elie Richa]

Hello.

I have been working on SMP support for the MPC8641D processor, so I have also 
worked on completing the SMP implementation of MPIC. I've been meaning to post a 
patch, but you beat me to it :)
I compared your implementation to mine, and it boils down to the same, except 
that I had overlooked the problem of IPIs when multiple CPUs are targeted.

I did some IPI tests with your code and it works fine generally, but some 
problems came up. It appears that the first time I trigger an IPI, CPU 0 always 
receives the IPI even if it wasn't targeted. The problem stops appearing after 
the first IPI.

It turns out that all IDEs are initialized to 0x1, which is forcing CPU 0 to 
receive the first IPI. IPI related IDEs should therefore be initialized to 0 in 
mpic_reset.

And I also have other comments. Some of them are below, and some others will 
come in a reply to another patch.

Elie

On 07/21/2011 03:27 AM, Alexander Graf wrote:
> @@ -934,6 +936,17 @@ static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
>                   reset_bit(&src->ipvp, IPVP_ACTIVITY);
>                   src->pending = 0;
>               }
> +
> +            if ((n_IRQ>= opp->irq_ipi0)&&   (n_IRQ<  (opp->irq_ipi0 + 4))) {

I think using (opp->irq_ipi0 + MAX_IPI) would be better?

> +                src->ide&= ~(1<<  idx);
> +                if (src->ide&&  !test_bit(&src->ipvp, IPVP_SENSE)) {
> +                    /* trigger on CPUs that didn't know about it yet */
> +                    openpic_set_irq(opp, n_IRQ, 1);
> +                    openpic_set_irq(opp, n_IRQ, 0);
> +                    /* if all CPUs knew about it, set active bit again */
> +                    set_bit(&src->ipvp, IPVP_ACTIVITY);
> +                }
> +            }
>           }
>           break;
>       case 0xB0: /* PEOI */

Also, in openpic_cpu_read_internal() , there's is the following code :

 > #if MAX_IPI > 0
 >     case 0x40: /* IDE */
 >     case 0x50:
 >         idx = (addr - 0x40) >> 4;
 >         retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE);
 >         break;
 > #endif

These are the IPI dispatch registers which are write only, so I suppose this 
shouldn't be here right?

Re: [Qemu-devel] [PATCH 08/23] PPC: Bump MPIC up to 32 supported CPUs

[Elie Richa]

On 07/21/2011 03:27 AM, Alexander Graf wrote:
> @@ -1288,7 +1288,7 @@ static void mpic_reset (void *opaque)
>
>       mpp->glbc = 0x80000000;
>       /* Initialise controller registers */
> -    mpp->frep = 0x004f0002;
> +    mpp->frep = 0x004f0002 | ((MAX_CPU - 1)<<  8);

Should we really report the maximum supported number of CPUs or the actual number?
Several processor manuals state that it is the number of physically present CPUs 
that is reported (-1 of course).
In that case, the following would do?
        mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1)<<  8);

>       mpp->veni = VENI;
>       mpp->pint = 0x00000000;
>       mpp->spve = 0x0000FFFF;
> @@ -1685,10 +1685,6 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
>           {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
>       };
>
> -    /* XXX: for now, only one CPU is supported */
> -    if (nb_cpus != 1)
> -        return NULL;
> -
>       mpp = qemu_mallocz(sizeof(openpic_t));
>
>       for (i = 0; i<  sizeof(list)/sizeof(list[0]); i++) {

Re: [Qemu-devel] [PATCH 06/23] PPC: Fix IPI support in MPIC

[Alexander Graf]

Hi :)

On 22.07.2011, at 16:08, Elie Richa wrote:

> Hello.
> 
> I have been working on SMP support for the MPC8641D processor, so I have also worked on completing the SMP implementation of MPIC. I've been meaning to post a patch, but you beat me to it :)

Ah, very nice! It's great to see more people interested in this.

> I compared your implementation to mine, and it boils down to the same, except that I had overlooked the problem of IPIs when multiple CPUs are targeted.

That was the really hard part. Took me 2 days to figure out how to route those properly internally :(.

> I did some IPI tests with your code and it works fine generally, but some problems came up. It appears that the first time I trigger an IPI, CPU 0 always receives the IPI even if it wasn't targeted. The problem stops appearing after the first IPI.
> 
> It turns out that all IDEs are initialized to 0x1, which is forcing CPU 0 to receive the first IPI. IPI related IDEs should therefore be initialized to 0 in mpic_reset.

Nice catch! You're right - we should just initialize the IPI IDE registers to 0.

> 
> And I also have other comments. Some of them are below, and some others will come in a reply to another patch.
> 
> Elie
> 
> On 07/21/2011 03:27 AM, Alexander Graf wrote:
>> @@ -934,6 +936,17 @@ static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
>>                  reset_bit(&src->ipvp, IPVP_ACTIVITY);
>>                  src->pending = 0;
>>              }
>> +
>> +            if ((n_IRQ>= opp->irq_ipi0)&&   (n_IRQ<  (opp->irq_ipi0 + 4))) {
> 
> I think using (opp->irq_ipi0 + MAX_IPI) would be better?

Yes, totally. Must have overlooked this :).

> 
>> +                src->ide&= ~(1<<  idx);
>> +                if (src->ide&&  !test_bit(&src->ipvp, IPVP_SENSE)) {
>> +                    /* trigger on CPUs that didn't know about it yet */
>> +                    openpic_set_irq(opp, n_IRQ, 1);
>> +                    openpic_set_irq(opp, n_IRQ, 0);
>> +                    /* if all CPUs knew about it, set active bit again */
>> +                    set_bit(&src->ipvp, IPVP_ACTIVITY);
>> +                }
>> +            }
>>          }
>>          break;
>>      case 0xB0: /* PEOI */
> 
> Also, in openpic_cpu_read_internal() , there's is the following code :
> 
> > #if MAX_IPI > 0
> >     case 0x40: /* IDE */
> >     case 0x50:
> >         idx = (addr - 0x40) >> 4;
> >         retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE);
> >         break;
> > #endif
> 
> These are the IPI dispatch registers which are write only, so I suppose this shouldn't be here right?

The code was there long before me :). No idea why it is there though - it tries to read out the IDE register for 2 IPIs. Maybe it was read-write in early versions of MPIC? Scott, any idea?


Alex

Re: [Qemu-devel] [PATCH 08/23] PPC: Bump MPIC up to 32 supported CPUs

[Alexander Graf]

On 22.07.2011, at 16:10, Elie Richa wrote:

> 
> On 07/21/2011 03:27 AM, Alexander Graf wrote:
>> @@ -1288,7 +1288,7 @@ static void mpic_reset (void *opaque)
>> 
>>      mpp->glbc = 0x80000000;
>>      /* Initialise controller registers */
>> -    mpp->frep = 0x004f0002;
>> +    mpp->frep = 0x004f0002 | ((MAX_CPU - 1)<<  8);
> 
> Should we really report the maximum supported number of CPUs or the actual number?
> Several processor manuals state that it is the number of physically present CPUs that is reported (-1 of course).
> In that case, the following would do?
>       mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1)<<  8);

Good idea. Will change :)


Alex

Re: [Qemu-devel] [PATCH 06/23] PPC: Fix IPI support in MPIC

[Scott Wood]

On Fri, 22 Jul 2011 17:01:11 +0200
Alexander Graf <agraf@suse.de> wrote:

> On 22.07.2011, at 16:08, Elie Richa wrote:
> 
> > > #if MAX_IPI > 0
> > >     case 0x40: /* IDE */
> > >     case 0x50:
> > >         idx = (addr - 0x40) >> 4;
> > >         retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE);
> > >         break;
> > > #endif
> > 
> > These are the IPI dispatch registers which are write only, so I suppose this shouldn't be here right?
> 
> The code was there long before me :). No idea why it is there though - it tries to read out the IDE register for 2 IPIs. Maybe it was read-write in early versions of MPIC? Scott, any idea?

I don't know about early MPICs, but I don't know how you'd even define that
register for read -- it's a command, not state.

I suspect it's just a bug -- especially given the initialization to 1,
which suggests the author saw it as just another destination register.

-Scott