From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:52238) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qji3M-0002DA-2E for qemu-devel@nongnu.org; Wed, 20 Jul 2011 21:27:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qji39-0003qz-S9 for qemu-devel@nongnu.org; Wed, 20 Jul 2011 21:27:50 -0400 Received: from cantor2.suse.de ([195.135.220.15]:57997 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qji38-0003pt-N0 for qemu-devel@nongnu.org; Wed, 20 Jul 2011 21:27:38 -0400 From: Alexander Graf Date: Thu, 21 Jul 2011 03:27:19 +0200 Message-Id: <1311211654-14326-9-git-send-email-agraf@suse.de> In-Reply-To: <1311211654-14326-1-git-send-email-agraf@suse.de> References: <1311211654-14326-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 08/23] PPC: Bump MPIC up to 32 supported CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU-devel Developers Cc: Scott Wood The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in the code exporting the numbers out and fix an integer overflow while at it. Signed-off-by: Alexander Graf --- hw/openpic.c | 10 +++------- 1 files changed, 3 insertions(+), 7 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 6630206..a8d7824 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -63,7 +63,7 @@ #elif defined(USE_MPCxxx) -#define MAX_CPU 2 +#define MAX_CPU 32 #define MAX_IRQ 128 #define MAX_DBL 0 #define MAX_MBX 0 @@ -507,7 +507,7 @@ static inline void write_IRQreg (openpic_t *opp, int n_IRQ, break; case IRQ_IDE: tmp = val & 0xC0000000; - tmp |= val & ((1 << MAX_CPU) - 1); + tmp |= val & ((1ULL << MAX_CPU) - 1); opp->src[n_IRQ].ide = tmp; DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide); break; @@ -1288,7 +1288,7 @@ static void mpic_reset (void *opaque) mpp->glbc = 0x80000000; /* Initialise controller registers */ - mpp->frep = 0x004f0002; + mpp->frep = 0x004f0002 | ((MAX_CPU - 1) << 8); mpp->veni = VENI; mpp->pint = 0x00000000; mpp->spve = 0x0000FFFF; @@ -1685,10 +1685,6 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus, {mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE}, }; - /* XXX: for now, only one CPU is supported */ - if (nb_cpus != 1) - return NULL; - mpp = qemu_mallocz(sizeof(openpic_t)); for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) { -- 1.6.0.2