From: Tsuneo Saito <tsnsaito@gmail.com>
To: qemu-devel@nongnu.org
Cc: Tsuneo Saito <tsnsaito@gmail.com>
Subject: [Qemu-devel] [PATCH 1/7] SPARC64: TTE bits cleanup
Date: Fri, 22 Jul 2011 00:16:27 +0900 [thread overview]
Message-ID: <1311261393-47400-2-git-send-email-tsnsaito@gmail.com> (raw)
In-Reply-To: <1311261393-47400-1-git-send-email-tsnsaito@gmail.com>
Add macros for TTE bits and modify to use macros instead of
magic numbers.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
target-sparc/cpu.h | 7 +++++++
target-sparc/helper.c | 35 +++++++++++++++++++----------------
2 files changed, 26 insertions(+), 16 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 0084b67..b2160e9 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -292,16 +292,23 @@ enum {
#define TTE_VALID_BIT (1ULL << 63)
#define TTE_USED_BIT (1ULL << 41)
#define TTE_LOCKED_BIT (1ULL << 6)
+#define TTE_PRIV_BIT (1ULL << 2)
+#define TTE_W_OK_BIT (1ULL << 1)
#define TTE_GLOBAL_BIT (1ULL << 0)
#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
+#define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
+#define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
#define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
+#define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
+#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
+
typedef struct SparcTLBEntry {
uint64_t tag;
uint64_t tte;
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 7eea1ac..0a4cfc5 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -378,7 +378,7 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
{
uint64_t mask;
- switch ((tlb->tte >> 61) & 3) {
+ switch (TTE_PGSIZE(tlb->tte)) {
default:
case 0x0: // 8k
mask = 0xffffffffffffe000ULL;
@@ -445,14 +445,14 @@ static int get_physical_address_data(CPUState *env,
uint8_t fault_type = 0;
// access ok?
- if ((env->dtlb[i].tte & 0x4) && is_user) {
+ if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
fault_type |= 1; /* privilege violation */
env->exception_index = TT_DFAULT;
DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64
" mmu_idx=%d tl=%d\n",
address, context, mmu_idx, env->tl);
- } else if (!(env->dtlb[i].tte & 0x2) && (rw == 1)) {
+ } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
env->exception_index = TT_DPROT;
DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64
@@ -460,8 +460,9 @@ static int get_physical_address_data(CPUState *env,
address, context, mmu_idx, env->tl);
} else {
*prot = PAGE_READ;
- if (env->dtlb[i].tte & 0x2)
+ if (TTE_IS_W_OK(env->dtlb[i].tte)) {
*prot |= PAGE_WRITE;
+ }
TTE_SET_USED(env->dtlb[i].tte);
@@ -522,7 +523,7 @@ static int get_physical_address_code(CPUState *env,
if (ultrasparc_tag_match(&env->itlb[i],
address, context, physical)) {
// access ok?
- if ((env->itlb[i].tte & 0x4) && is_user) {
+ if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
if (env->immu.sfsr) /* Fault status register */
env->immu.sfsr = 2; /* overflow (not read before
another fault) */
@@ -632,7 +633,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
} else {
(*cpu_fprintf)(f, "DMMU dump\n");
for (i = 0; i < 64; i++) {
- switch ((env->dtlb[i].tte >> 61) & 3) {
+ switch (TTE_PGSIZE(env->dtlb[i].tte)) {
default:
case 0x0:
mask = " 8k";
@@ -647,16 +648,17 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
mask = " 4M";
break;
}
- if ((env->dtlb[i].tte & 0x8000000000000000ULL) != 0) {
+ if (TTE_IS_VALID(env->dtlb[i].tte)) {
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %" PRIx64
", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
i,
env->dtlb[i].tag & (uint64_t)~0x1fffULL,
- env->dtlb[i].tte & (uint64_t)0x1ffffffe000ULL,
+ TTE_PA(env->dtlb[i].tte),
mask,
- env->dtlb[i].tte & 0x4? "priv": "user",
- env->dtlb[i].tte & 0x2? "RW": "RO",
- env->dtlb[i].tte & 0x40? "locked": "unlocked",
+ TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user",
+ TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO",
+ TTE_IS_LOCKED(env->dtlb[i].tte) ?
+ "locked" : "unlocked",
env->dtlb[i].tag & (uint64_t)0x1fffULL,
TTE_IS_GLOBAL(env->dtlb[i].tte)?
"global" : "local");
@@ -668,7 +670,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
} else {
(*cpu_fprintf)(f, "IMMU dump\n");
for (i = 0; i < 64; i++) {
- switch ((env->itlb[i].tte >> 61) & 3) {
+ switch (TTE_PGSIZE(env->itlb[i].tte)) {
default:
case 0x0:
mask = " 8k";
@@ -683,15 +685,16 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
mask = " 4M";
break;
}
- if ((env->itlb[i].tte & 0x8000000000000000ULL) != 0) {
+ if (TTE_IS_VALID(env->itlb[i].tte)) {
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %" PRIx64
", %s, %s, %s, ctx %" PRId64 " %s\n",
i,
env->itlb[i].tag & (uint64_t)~0x1fffULL,
- env->itlb[i].tte & (uint64_t)0x1ffffffe000ULL,
+ TTE_PA(env->itlb[i].tte),
mask,
- env->itlb[i].tte & 0x4? "priv": "user",
- env->itlb[i].tte & 0x40? "locked": "unlocked",
+ TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user",
+ TTE_IS_LOCKED(env->itlb[i].tte) ?
+ "locked" : "unlocked",
env->itlb[i].tag & (uint64_t)0x1fffULL,
TTE_IS_GLOBAL(env->itlb[i].tte)?
"global" : "local");
--
1.7.5.4
next prev parent reply other threads:[~2011-07-21 15:20 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-21 15:16 [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Tsuneo Saito
2011-07-21 15:16 ` Tsuneo Saito [this message]
2011-07-21 15:16 ` [Qemu-devel] [PATCH 2/7] SPARC64: SFSR cleanup and fix Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 3/7] SPARC64: introduce a convenience function for getting physical addresses Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 4/7] SPARC64: split cpu_get_phys_page_debug() from cpu_get_phys_page_nofault() Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 5/7] SPARC64: fix fault status overwritten on nonfaulting load Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 6/7] SPARC64: implement MMU miss traps on nonfaulting loads Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 7/7] SPARC64: implement addtional MMU faults related to nonfaulting load Tsuneo Saito
2011-07-21 20:15 ` [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Blue Swirl
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