* [Qemu-devel] [PATCH 1/7] SPARC64: TTE bits cleanup
2011-07-21 15:16 [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Tsuneo Saito
@ 2011-07-21 15:16 ` Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 2/7] SPARC64: SFSR cleanup and fix Tsuneo Saito
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Tsuneo Saito @ 2011-07-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Tsuneo Saito
Add macros for TTE bits and modify to use macros instead of
magic numbers.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
target-sparc/cpu.h | 7 +++++++
target-sparc/helper.c | 35 +++++++++++++++++++----------------
2 files changed, 26 insertions(+), 16 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 0084b67..b2160e9 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -292,16 +292,23 @@ enum {
#define TTE_VALID_BIT (1ULL << 63)
#define TTE_USED_BIT (1ULL << 41)
#define TTE_LOCKED_BIT (1ULL << 6)
+#define TTE_PRIV_BIT (1ULL << 2)
+#define TTE_W_OK_BIT (1ULL << 1)
#define TTE_GLOBAL_BIT (1ULL << 0)
#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
+#define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
+#define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
#define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
+#define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
+#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
+
typedef struct SparcTLBEntry {
uint64_t tag;
uint64_t tte;
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 7eea1ac..0a4cfc5 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -378,7 +378,7 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
{
uint64_t mask;
- switch ((tlb->tte >> 61) & 3) {
+ switch (TTE_PGSIZE(tlb->tte)) {
default:
case 0x0: // 8k
mask = 0xffffffffffffe000ULL;
@@ -445,14 +445,14 @@ static int get_physical_address_data(CPUState *env,
uint8_t fault_type = 0;
// access ok?
- if ((env->dtlb[i].tte & 0x4) && is_user) {
+ if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
fault_type |= 1; /* privilege violation */
env->exception_index = TT_DFAULT;
DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64
" mmu_idx=%d tl=%d\n",
address, context, mmu_idx, env->tl);
- } else if (!(env->dtlb[i].tte & 0x2) && (rw == 1)) {
+ } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
env->exception_index = TT_DPROT;
DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64
@@ -460,8 +460,9 @@ static int get_physical_address_data(CPUState *env,
address, context, mmu_idx, env->tl);
} else {
*prot = PAGE_READ;
- if (env->dtlb[i].tte & 0x2)
+ if (TTE_IS_W_OK(env->dtlb[i].tte)) {
*prot |= PAGE_WRITE;
+ }
TTE_SET_USED(env->dtlb[i].tte);
@@ -522,7 +523,7 @@ static int get_physical_address_code(CPUState *env,
if (ultrasparc_tag_match(&env->itlb[i],
address, context, physical)) {
// access ok?
- if ((env->itlb[i].tte & 0x4) && is_user) {
+ if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
if (env->immu.sfsr) /* Fault status register */
env->immu.sfsr = 2; /* overflow (not read before
another fault) */
@@ -632,7 +633,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
} else {
(*cpu_fprintf)(f, "DMMU dump\n");
for (i = 0; i < 64; i++) {
- switch ((env->dtlb[i].tte >> 61) & 3) {
+ switch (TTE_PGSIZE(env->dtlb[i].tte)) {
default:
case 0x0:
mask = " 8k";
@@ -647,16 +648,17 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
mask = " 4M";
break;
}
- if ((env->dtlb[i].tte & 0x8000000000000000ULL) != 0) {
+ if (TTE_IS_VALID(env->dtlb[i].tte)) {
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %" PRIx64
", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
i,
env->dtlb[i].tag & (uint64_t)~0x1fffULL,
- env->dtlb[i].tte & (uint64_t)0x1ffffffe000ULL,
+ TTE_PA(env->dtlb[i].tte),
mask,
- env->dtlb[i].tte & 0x4? "priv": "user",
- env->dtlb[i].tte & 0x2? "RW": "RO",
- env->dtlb[i].tte & 0x40? "locked": "unlocked",
+ TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user",
+ TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO",
+ TTE_IS_LOCKED(env->dtlb[i].tte) ?
+ "locked" : "unlocked",
env->dtlb[i].tag & (uint64_t)0x1fffULL,
TTE_IS_GLOBAL(env->dtlb[i].tte)?
"global" : "local");
@@ -668,7 +670,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
} else {
(*cpu_fprintf)(f, "IMMU dump\n");
for (i = 0; i < 64; i++) {
- switch ((env->itlb[i].tte >> 61) & 3) {
+ switch (TTE_PGSIZE(env->itlb[i].tte)) {
default:
case 0x0:
mask = " 8k";
@@ -683,15 +685,16 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
mask = " 4M";
break;
}
- if ((env->itlb[i].tte & 0x8000000000000000ULL) != 0) {
+ if (TTE_IS_VALID(env->itlb[i].tte)) {
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %" PRIx64
", %s, %s, %s, ctx %" PRId64 " %s\n",
i,
env->itlb[i].tag & (uint64_t)~0x1fffULL,
- env->itlb[i].tte & (uint64_t)0x1ffffffe000ULL,
+ TTE_PA(env->itlb[i].tte),
mask,
- env->itlb[i].tte & 0x4? "priv": "user",
- env->itlb[i].tte & 0x40? "locked": "unlocked",
+ TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user",
+ TTE_IS_LOCKED(env->itlb[i].tte) ?
+ "locked" : "unlocked",
env->itlb[i].tag & (uint64_t)0x1fffULL,
TTE_IS_GLOBAL(env->itlb[i].tte)?
"global" : "local");
--
1.7.5.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH 2/7] SPARC64: SFSR cleanup and fix
2011-07-21 15:16 [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 1/7] SPARC64: TTE bits cleanup Tsuneo Saito
@ 2011-07-21 15:16 ` Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 3/7] SPARC64: introduce a convenience function for getting physical addresses Tsuneo Saito
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Tsuneo Saito @ 2011-07-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Tsuneo Saito
Add macros for SFSR fields and use macros instead of magic numbers.
Also fix the update of the register fields on MMU faults.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
target-sparc/cpu.h | 22 ++++++++++++++++++++
target-sparc/helper.c | 52 +++++++++++++++++++++++++++++++++++++-----------
2 files changed, 62 insertions(+), 12 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index b2160e9..348858e 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -309,6 +309,28 @@ enum {
#define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
#define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
+#define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */
+#define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */
+#define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */
+#define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */
+#define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */
+#define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */
+#define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */
+#define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */
+#define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */
+#define SFSR_PR_BIT (1ULL << 3) /* privilege mode */
+#define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */
+#define SFSR_OW_BIT (1ULL << 1) /* status overwritten */
+#define SFSR_VALID_BIT (1ULL << 0) /* status valid */
+
+#define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */
+#define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT)
+#define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */
+#define SFSR_CT_SECONDARY (1ULL << 4)
+#define SFSR_CT_NUCLEUS (2ULL << 4)
+#define SFSR_CT_NOTRANS (3ULL << 4)
+#define SFSR_CT_MASK (3ULL << 4)
+
typedef struct SparcTLBEntry {
uint64_t tag;
uint64_t tte;
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 0a4cfc5..f9b7fe2 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -413,6 +413,7 @@ static int get_physical_address_data(CPUState *env,
{
unsigned int i;
uint64_t context;
+ uint64_t sfsr = 0;
int is_user = (mmu_idx == MMU_USER_IDX ||
mmu_idx == MMU_USER_SECONDARY_IDX);
@@ -427,26 +428,32 @@ static int get_physical_address_data(CPUState *env,
case MMU_USER_IDX:
case MMU_KERNEL_IDX:
context = env->dmmu.mmu_primary_context & 0x1fff;
+ sfsr |= SFSR_CT_PRIMARY;
break;
case MMU_USER_SECONDARY_IDX:
case MMU_KERNEL_SECONDARY_IDX:
context = env->dmmu.mmu_secondary_context & 0x1fff;
+ sfsr |= SFSR_CT_SECONDARY;
break;
case MMU_NUCLEUS_IDX:
+ sfsr |= SFSR_CT_NUCLEUS;
+ /* FALLTHRU */
default:
context = 0;
break;
}
+ if (rw == 1) {
+ sfsr |= SFSR_WRITE_BIT;
+ }
+
for (i = 0; i < 64; i++) {
// ctx match, vaddr match, valid?
if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
- uint8_t fault_type = 0;
-
// access ok?
if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
- fault_type |= 1; /* privilege violation */
+ sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
env->exception_index = TT_DFAULT;
DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64
@@ -469,13 +476,17 @@ static int get_physical_address_data(CPUState *env,
return 0;
}
- if (env->dmmu.sfsr & 1) /* Fault status register */
- env->dmmu.sfsr = 2; /* overflow (not read before
- another fault) */
+ if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */
+ sfsr |= SFSR_OW_BIT; /* overflow (not read before
+ another fault) */
+ }
- env->dmmu.sfsr |= (is_user << 3) | ((rw == 1) << 2) | 1;
+ if (env->pstate & PS_PRIV) {
+ sfsr |= SFSR_PR_BIT;
+ }
- env->dmmu.sfsr |= (fault_type << 7);
+ /* FIXME: ASI field in SFSR must be set */
+ env->dmmu.sfsr = sfsr | SFSR_VALID_BIT;
env->dmmu.sfar = address; /* Fault address register */
@@ -488,6 +499,11 @@ static int get_physical_address_data(CPUState *env,
DPRINTF_MMU("DMISS at %" PRIx64 " context %" PRIx64 "\n",
address, context);
+ /*
+ * On MMU misses:
+ * - UltraSPARC IIi: SFSR and SFAR unmodified
+ * - JPS1: SFAR updated and some fields of SFSR updated
+ */
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
env->exception_index = TT_DMISS;
return 1;
@@ -524,10 +540,22 @@ static int get_physical_address_code(CPUState *env,
address, context, physical)) {
// access ok?
if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
- if (env->immu.sfsr) /* Fault status register */
- env->immu.sfsr = 2; /* overflow (not read before
- another fault) */
- env->immu.sfsr |= (is_user << 3) | 1;
+ /* Fault status register */
+ if (env->immu.sfsr & SFSR_VALID_BIT) {
+ env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before
+ another fault) */
+ } else {
+ env->immu.sfsr = 0;
+ }
+ if (env->pstate & PS_PRIV) {
+ env->immu.sfsr |= SFSR_PR_BIT;
+ }
+ if (env->tl > 0) {
+ env->immu.sfsr |= SFSR_CT_NUCLEUS;
+ }
+
+ /* FIXME: ASI field in SFSR must be set */
+ env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT;
env->exception_index = TT_TFAULT;
env->immu.tag_access = (address & ~0x1fffULL) | context;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH 3/7] SPARC64: introduce a convenience function for getting physical addresses
2011-07-21 15:16 [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 1/7] SPARC64: TTE bits cleanup Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 2/7] SPARC64: SFSR cleanup and fix Tsuneo Saito
@ 2011-07-21 15:16 ` Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 4/7] SPARC64: split cpu_get_phys_page_debug() from cpu_get_phys_page_nofault() Tsuneo Saito
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Tsuneo Saito @ 2011-07-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Tsuneo Saito
Introduce cpu_sparc_get_phys_page() to be used as a help for splitting
cpu_get_phys_page_debug() from cpu_get_phys_page_nofault().
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
target-sparc/helper.c | 20 ++++++++++++++------
1 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index f9b7fe2..9acbcae 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -736,18 +736,26 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
#if !defined(CONFIG_USER_ONLY)
+static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys,
+ target_ulong addr, int rw, int mmu_idx)
+{
+ target_ulong page_size;
+ int prot, access_index;
+
+ return get_physical_address(env, phys, &prot, &access_index, addr, rw,
+ mmu_idx, &page_size);
+}
+
target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
int mmu_idx)
{
target_phys_addr_t phys_addr;
- target_ulong page_size;
- int prot, access_index;
- if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
- mmu_idx, &page_size) != 0)
- if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
- 0, mmu_idx, &page_size) != 0)
+ if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
+ if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
return -1;
+ }
+ }
if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
return -1;
return phys_addr;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH 4/7] SPARC64: split cpu_get_phys_page_debug() from cpu_get_phys_page_nofault()
2011-07-21 15:16 [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Tsuneo Saito
` (2 preceding siblings ...)
2011-07-21 15:16 ` [Qemu-devel] [PATCH 3/7] SPARC64: introduce a convenience function for getting physical addresses Tsuneo Saito
@ 2011-07-21 15:16 ` Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 5/7] SPARC64: fix fault status overwritten on nonfaulting load Tsuneo Saito
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Tsuneo Saito @ 2011-07-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Tsuneo Saito
This patch makes cpu_get_phys_page_debug() independent from
cpu_get_phys_page_nofault() in advance of implementing nonfaulting load.
This also modifies cpu_get_phys_page_nofault() to be compiled only on
TARGET_SPARC64 because it is not required on SPARC32.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
target-sparc/cpu.h | 2 ++
target-sparc/helper.c | 15 ++++++++++++++-
2 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 348858e..f4eeff5 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -541,10 +541,12 @@ static inline int tlb_compare_context(const SparcTLBEntry *tlb,
#if !defined(CONFIG_USER_ONLY)
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int is_asi, int size);
+#if defined(TARGET_SPARC64)
target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
int mmu_idx);
#endif
+#endif
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_init cpu_sparc_init
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 9acbcae..cb8d706 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -746,6 +746,7 @@ static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys,
mmu_idx, &page_size);
}
+#if defined(TARGET_SPARC64)
target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
int mmu_idx)
{
@@ -760,10 +761,22 @@ target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
return -1;
return phys_addr;
}
+#endif
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
- return cpu_get_phys_page_nofault(env, addr, cpu_mmu_index(env));
+ target_phys_addr_t phys_addr;
+ int mmu_idx = cpu_mmu_index(env);
+
+ if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
+ if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
+ return -1;
+ }
+ }
+ if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED) {
+ return -1;
+ }
+ return phys_addr;
}
#endif
--
1.7.5.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH 5/7] SPARC64: fix fault status overwritten on nonfaulting load
2011-07-21 15:16 [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Tsuneo Saito
` (3 preceding siblings ...)
2011-07-21 15:16 ` [Qemu-devel] [PATCH 4/7] SPARC64: split cpu_get_phys_page_debug() from cpu_get_phys_page_nofault() Tsuneo Saito
@ 2011-07-21 15:16 ` Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 6/7] SPARC64: implement MMU miss traps on nonfaulting loads Tsuneo Saito
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Tsuneo Saito @ 2011-07-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Tsuneo Saito
cpu_get_phys_page_nofault() calls get_physical_address() twice,
that results in overwriting the fault status in the SFSR.
We need this change in order for nonfaulting loads to raising MMU faults
as normal loads do.
Also removed the call to cpu_get_physical_page_desc() since we are
going to modify nonfaulting loads raising MMU faults.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
target-sparc/helper.c | 8 ++------
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index cb8d706..b6e62a7 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -752,13 +752,9 @@ target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
{
target_phys_addr_t phys_addr;
- if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
- if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
- return -1;
- }
- }
- if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
+ if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
return -1;
+ }
return phys_addr;
}
#endif
--
1.7.5.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH 6/7] SPARC64: implement MMU miss traps on nonfaulting loads
2011-07-21 15:16 [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Tsuneo Saito
` (4 preceding siblings ...)
2011-07-21 15:16 ` [Qemu-devel] [PATCH 5/7] SPARC64: fix fault status overwritten on nonfaulting load Tsuneo Saito
@ 2011-07-21 15:16 ` Tsuneo Saito
2011-07-21 15:16 ` [Qemu-devel] [PATCH 7/7] SPARC64: implement addtional MMU faults related to nonfaulting load Tsuneo Saito
2011-07-21 20:15 ` [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Blue Swirl
7 siblings, 0 replies; 9+ messages in thread
From: Tsuneo Saito @ 2011-07-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Tsuneo Saito
Nonfaulting loads should raise fast_data_access_MMU_miss traps as
normal loads do. It is up to the guest OS kernel that detect MMU misses
on nonfaulting load instructions and make them complete without signaling.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
target-sparc/op_helper.c | 36 ++++++++++++++++++++----------------
1 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 3b7f9ca..8962e38 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -2567,24 +2567,30 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
helper_check_align(addr, size - 1);
addr = asi_address_mask(env, asi, addr);
- switch (asi) {
- case 0x82: // Primary no-fault
- case 0x8a: // Primary no-fault LE
- case 0x83: // Secondary no-fault
- case 0x8b: // Secondary no-fault LE
- {
- /* secondary space access has lowest asi bit equal to 1 */
- int access_mmu_idx = ( asi & 1 ) ? MMU_KERNEL_IDX
- : MMU_KERNEL_SECONDARY_IDX;
+ /* process nonfaulting loads first */
+ if ((asi & 0xf6) == 0x82) {
+ int mmu_idx;
+
+ /* secondary space access has lowest asi bit equal to 1 */
+ if (env->pstate & PS_PRIV) {
+ mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
+ } else {
+ mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
+ }
- if (cpu_get_phys_page_nofault(env, addr, access_mmu_idx) == -1ULL) {
+ if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
#ifdef DEBUG_ASI
- dump_asi("read ", last_addr, asi, size, ret);
+ dump_asi("read ", last_addr, asi, size, ret);
#endif
- return 0;
- }
+ /* env->exception_index is set in get_physical_address_data(). */
+ raise_exception(env->exception_index);
}
- // Fall through
+
+ /* convert nonfaulting load ASIs to normal load ASIs */
+ asi &= ~0x02;
+ }
+
+ switch (asi) {
case 0x10: // As if user primary
case 0x11: // As if user secondary
case 0x18: // As if user primary LE
@@ -2862,8 +2868,6 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0x1d: // Bypass, non-cacheable LE
case 0x88: // Primary LE
case 0x89: // Secondary LE
- case 0x8a: // Primary no-fault LE
- case 0x8b: // Secondary no-fault LE
switch(size) {
case 2:
ret = bswap16(ret);
--
1.7.5.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH 7/7] SPARC64: implement addtional MMU faults related to nonfaulting load
2011-07-21 15:16 [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Tsuneo Saito
` (5 preceding siblings ...)
2011-07-21 15:16 ` [Qemu-devel] [PATCH 6/7] SPARC64: implement MMU miss traps on nonfaulting loads Tsuneo Saito
@ 2011-07-21 15:16 ` Tsuneo Saito
2011-07-21 20:15 ` [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Blue Swirl
7 siblings, 0 replies; 9+ messages in thread
From: Tsuneo Saito @ 2011-07-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Tsuneo Saito
This patch implements MMU faults caused by TTE.NFO and TTE.E:
- access other than nonfaulting load to a page marked NFO should
raise data_access_exception
- nonfaulting load to a page marked with E bit should raise
data_access_exception
To distinguish nonfaulting loads, this patch extends (abuses?) the rw
argument of get_physical_address_data(). rw is set to 4 on nonfaulting
loads.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
---
target-sparc/cpu.h | 4 ++++
target-sparc/helper.c | 29 ++++++++++++++++++++++++++---
2 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index f4eeff5..a51863c 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -290,15 +290,19 @@ enum {
#endif
#define TTE_VALID_BIT (1ULL << 63)
+#define TTE_NFO_BIT (1ULL << 60)
#define TTE_USED_BIT (1ULL << 41)
#define TTE_LOCKED_BIT (1ULL << 6)
+#define TTE_SIDEEFFECT_BIT (1ULL << 3)
#define TTE_PRIV_BIT (1ULL << 2)
#define TTE_W_OK_BIT (1ULL << 1)
#define TTE_GLOBAL_BIT (1ULL << 0)
#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
+#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
+#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
#define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
#define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index b6e62a7..acc07f5 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -445,27 +445,50 @@ static int get_physical_address_data(CPUState *env,
if (rw == 1) {
sfsr |= SFSR_WRITE_BIT;
+ } else if (rw == 4) {
+ sfsr |= SFSR_NF_BIT;
}
for (i = 0; i < 64; i++) {
// ctx match, vaddr match, valid?
if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
+ int do_fault = 0;
// access ok?
+ /* multiple bits in SFSR.FT may be set on TT_DFAULT */
if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
+ do_fault = 1;
sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
- env->exception_index = TT_DFAULT;
DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64
" mmu_idx=%d tl=%d\n",
address, context, mmu_idx, env->tl);
+ }
+ if (rw == 4) {
+ if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) {
+ do_fault = 1;
+ sfsr |= SFSR_FT_NF_E_BIT;
+ }
+ } else {
+ if (TTE_IS_NFO(env->dtlb[i].tte)) {
+ do_fault = 1;
+ sfsr |= SFSR_FT_NFO_BIT;
+ }
+ }
+
+ if (do_fault) {
+ /* faults above are reported with TT_DFAULT. */
+ env->exception_index = TT_DFAULT;
} else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
+ do_fault = 1;
env->exception_index = TT_DPROT;
DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64
" mmu_idx=%d tl=%d\n",
address, context, mmu_idx, env->tl);
- } else {
+ }
+
+ if (!do_fault) {
*prot = PAGE_READ;
if (TTE_IS_W_OK(env->dtlb[i].tte)) {
*prot |= PAGE_WRITE;
@@ -752,7 +775,7 @@ target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
{
target_phys_addr_t phys_addr;
- if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
+ if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) {
return -1;
}
return phys_addr;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu
2011-07-21 15:16 [Qemu-devel] [PATCH 0/7] SPARC64: fix nonfaulting load on softmmu Tsuneo Saito
` (6 preceding siblings ...)
2011-07-21 15:16 ` [Qemu-devel] [PATCH 7/7] SPARC64: implement addtional MMU faults related to nonfaulting load Tsuneo Saito
@ 2011-07-21 20:15 ` Blue Swirl
7 siblings, 0 replies; 9+ messages in thread
From: Blue Swirl @ 2011-07-21 20:15 UTC (permalink / raw)
To: Tsuneo Saito; +Cc: qemu-devel
Thanks, applied all.
On Thu, Jul 21, 2011 at 6:16 PM, Tsuneo Saito <tsnsaito@gmail.com> wrote:
> This patch series fixes nonfaulting load ASIs and traps related to them.
> According to "8.3.4 Non-Faulting Load" in the UltraSPARC-IIi User's Manual,
> a CPU should raise a TLB miss to the system software if the load is for
> unmapped area:
> "When a non-faulting load encounters a TLB miss, the operating system
> should attempt to translate the page. If the translation results in
> an error (for example, address out of range), a 0 is returned and the
> load completes silently."
>
> The first 4 patches are not directly related to nonfaulting load
> but are cleanups and fixes for preparing for the fix. The next 2 patches
> fix the problem and the last one is for related faults other than
> the TLB miss.
>
> Tsuneo Saito (7):
> SPARC64: TTE bits cleanup
> SPARC64: SFSR cleanup and fix
> SPARC64: introduce a convenience function for getting physical
> addresses
> SPARC64: split cpu_get_phys_page_debug() from
> cpu_get_phys_page_nofault()
> SPARC64: fix fault status overwritten on nonfaulting load
> SPARC64: implement MMU miss traps on nonfaulting loads
> SPARC64: implement addtional MMU faults related to nonfaulting load
>
> target-sparc/cpu.h | 35 +++++++++++
> target-sparc/helper.c | 149 ++++++++++++++++++++++++++++++++++------------
> target-sparc/op_helper.c | 36 ++++++-----
> 3 files changed, 165 insertions(+), 55 deletions(-)
>
> --
> 1.7.5.4
>
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread