From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:55908) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QkRpr-0004Lz-FI for qemu-devel@nongnu.org; Fri, 22 Jul 2011 22:21:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QkRpq-0004RS-Gn for qemu-devel@nongnu.org; Fri, 22 Jul 2011 22:20:59 -0400 Received: from mail-pz0-f43.google.com ([209.85.210.43]:58490) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QkRpq-0004RE-8Y for qemu-devel@nongnu.org; Fri, 22 Jul 2011 22:20:58 -0400 Received: by pzk1 with SMTP id 1so4828422pzk.30 for ; Fri, 22 Jul 2011 19:20:57 -0700 (PDT) From: Tsuneo Saito Date: Sat, 23 Jul 2011 11:20:06 +0900 Message-Id: <1311387607-56720-2-git-send-email-tsnsaito@gmail.com> In-Reply-To: <1311387607-56720-1-git-send-email-tsnsaito@gmail.com> References: <1311387607-56720-1-git-send-email-tsnsaito@gmail.com> Subject: [Qemu-devel] [PATCH 1/2] SPARC64: fix fnor* and fnand* List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tsuneo Saito Fix the problem that result values are not assigned to the destination registers. Signed-off-by: Tsuneo Saito --- target-sparc/translate.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 15967c5..f68b3bc 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3980,14 +3980,15 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x062: /* VIS I fnor */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], + tcg_gen_nor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], cpu_fpr[DFPREG(rs2)]); - tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], + tcg_gen_nor_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], cpu_fpr[DFPREG(rs2) + 1]); break; case 0x063: /* VIS I fnors */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); + tcg_gen_nor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x064: /* VIS I fandnot2 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4047,14 +4048,15 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x06e: /* VIS I fnand */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], + tcg_gen_nand_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], cpu_fpr[DFPREG(rs2)]); - tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], + tcg_gen_nand_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], cpu_fpr[DFPREG(rs2) + 1]); break; case 0x06f: /* VIS I fnands */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); + tcg_gen_nand_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x070: /* VIS I fand */ CHECK_FPU_FEATURE(dc, VIS1); -- 1.7.5.4