From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:44256) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QkZml-0007mw-5m for qemu-devel@nongnu.org; Sat, 23 Jul 2011 06:50:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QkZmi-0005sx-DG for qemu-devel@nongnu.org; Sat, 23 Jul 2011 06:50:19 -0400 Received: from cantor2.suse.de ([195.135.220.15]:54476 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QkZmi-0005sW-7B for qemu-devel@nongnu.org; Sat, 23 Jul 2011 06:50:16 -0400 From: Alexander Graf Date: Sat, 23 Jul 2011 12:49:51 +0200 Message-Id: <1311418212-13356-8-git-send-email-agraf@suse.de> In-Reply-To: <1311418212-13356-1-git-send-email-agraf@suse.de> References: <1311418212-13356-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 07/28] PPC: MPIC: Fix CI bit definitions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU-devel Developers Cc: Scott Wood , Elie Richa The bit definitions for critical interrupt routing are in PowerPC order (most significant bit is 0), while we end up shifting it with normal bit order. Turn the numbers around so we actually end up fetching the right ones. Signed-off-by: Alexander Graf --- hw/openpic.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 3f50421..af07e13 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -131,11 +131,11 @@ enum { #define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) enum mpic_ide_bits { - IDR_EP = 0, - IDR_CI0 = 1, - IDR_CI1 = 2, - IDR_P1 = 30, - IDR_P0 = 31, + IDR_EP = 31, + IDR_CI0 = 30, + IDR_CI1 = 29, + IDR_P1 = 1, + IDR_P0 = 0, }; #else -- 1.6.0.2