From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59507) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QreMG-0005nd-5R for qemu-devel@nongnu.org; Thu, 11 Aug 2011 19:08:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QreMB-0004iX-PO for qemu-devel@nongnu.org; Thu, 11 Aug 2011 19:08:11 -0400 Received: from mail-qy0-f180.google.com ([209.85.216.180]:59464) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QreMB-0004hi-Jw for qemu-devel@nongnu.org; Thu, 11 Aug 2011 19:08:07 -0400 Received: by mail-qy0-f180.google.com with SMTP id 31so1610068qyk.4 for ; Thu, 11 Aug 2011 16:08:07 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 11 Aug 2011 16:07:17 -0700 Message-Id: <1313104041-1641-6-git-send-email-rth@twiddle.net> In-Reply-To: <1313104041-1641-1-git-send-email-rth@twiddle.net> References: <1313104041-1641-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 5/9] ppc405: Pass in address_space_mem to ppc405{cr, ep}_init. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: avi@redhat.com Signed-off-by: Richard Henderson --- hw/ppc405.h | 22 ++++++++++++---------- hw/ppc405_boards.c | 8 ++++---- hw/ppc405_uc.c | 30 ++++++++++++++++-------------- 3 files changed, 32 insertions(+), 28 deletions(-) diff --git a/hw/ppc405.h b/hw/ppc405.h index f0e81a6..d8fdf09 100644 --- a/hw/ppc405.h +++ b/hw/ppc405.h @@ -59,16 +59,18 @@ struct ppc4xx_bd_info_t { ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, uint32_t flags); -CPUState *ppc405cr_init (MemoryRegion ram_memories[4], - target_phys_addr_t ram_bases[4], - target_phys_addr_t ram_sizes[4], - uint32_t sysclk, qemu_irq **picp, - int do_init); -CPUState *ppc405ep_init (MemoryRegion ram_memories[2], - target_phys_addr_t ram_bases[2], - target_phys_addr_t ram_sizes[2], - uint32_t sysclk, qemu_irq **picp, - int do_init); +CPUState *ppc405cr_init(MemoryRegion *address_space_mem, + MemoryRegion ram_memories[4], + target_phys_addr_t ram_bases[4], + target_phys_addr_t ram_sizes[4], + uint32_t sysclk, qemu_irq **picp, + int do_init); +CPUState *ppc405ep_init(MemoryRegion *address_space_mem, + MemoryRegion ram_memories[2], + target_phys_addr_t ram_bases[2], + target_phys_addr_t ram_sizes[2], + uint32_t sysclk, qemu_irq **picp, + int do_init); /* IBM STBxxx microcontrollers */ CPUState *ppc_stb025_init (MemoryRegion ram_memories[2], target_phys_addr_t ram_bases[2], diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index 29de6c7..c696373 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -209,8 +209,8 @@ static void ref405ep_init (MemoryRegion *address_space_mem, #ifdef DEBUG_BOARD_INIT printf("%s: register cpu\n", __func__); #endif - env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic, - kernel_filename == NULL ? 0 : 1); + env = ppc405ep_init(address_space_mem, ram_memories, ram_bases, ram_sizes, + 33333333, &pic, kernel_filename == NULL ? 0 : 1); /* allocate SRAM */ sram_size = 512 * 1024; sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size); @@ -538,8 +538,8 @@ static void taihu_405ep_init(MemoryRegion *address_space_mem, #ifdef DEBUG_BOARD_INIT printf("%s: register cpu\n", __func__); #endif - ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic, - kernel_filename == NULL ? 0 : 1); + ppc405ep_init(address_space_mem, ram_memories, ram_bases, ram_sizes, + 33333333, &pic, kernel_filename == NULL ? 0 : 1); /* allocate and load BIOS */ #ifdef DEBUG_BOARD_INIT printf("%s: register BIOS\n", __func__); diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index ffd806b..cbe7a18 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -2107,11 +2107,12 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], qemu_register_reset(ppc405cr_cpc_reset, cpc); } -CPUState *ppc405cr_init (MemoryRegion ram_memories[4], - target_phys_addr_t ram_bases[4], - target_phys_addr_t ram_sizes[4], - uint32_t sysclk, qemu_irq **picp, - int do_init) +CPUState *ppc405cr_init(MemoryRegion *address_space_mem, + MemoryRegion ram_memories[4], + target_phys_addr_t ram_bases[4], + target_phys_addr_t ram_sizes[4], + uint32_t sysclk, qemu_irq **picp, + int do_init) { clk_setup_t clk_setup[PPC405CR_CLK_NB]; qemu_irq dma_irqs[4]; @@ -2149,12 +2150,12 @@ CPUState *ppc405cr_init (MemoryRegion ram_memories[4], ppc405_dma_init(env, dma_irqs); /* Serial ports */ if (serial_hds[0] != NULL) { - serial_mm_init(get_system_memory(), 0xef600300, 0, pic[0], + serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, serial_hds[0], DEVICE_BIG_ENDIAN); } if (serial_hds[1] != NULL) { - serial_mm_init(get_system_memory(), 0xef600400, 0, pic[1], + serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, serial_hds[1], DEVICE_BIG_ENDIAN); } @@ -2455,11 +2456,12 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], #endif } -CPUState *ppc405ep_init (MemoryRegion ram_memories[2], - target_phys_addr_t ram_bases[2], - target_phys_addr_t ram_sizes[2], - uint32_t sysclk, qemu_irq **picp, - int do_init) +CPUState *ppc405ep_init(MemoryRegion *address_space_mem, + MemoryRegion ram_memories[2], + target_phys_addr_t ram_bases[2], + target_phys_addr_t ram_sizes[2], + uint32_t sysclk, qemu_irq **picp, + int do_init) { clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; @@ -2506,12 +2508,12 @@ CPUState *ppc405ep_init (MemoryRegion ram_memories[2], ppc405_gpio_init(0xef600700); /* Serial ports */ if (serial_hds[0] != NULL) { - serial_mm_init(get_system_memory(), 0xef600300, 0, pic[0], + serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, serial_hds[0], DEVICE_BIG_ENDIAN); } if (serial_hds[1] != NULL) { - serial_mm_init(get_system_memory(), 0xef600400, 0, pic[1], + serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, serial_hds[1], DEVICE_BIG_ENDIAN); } -- 1.7.6